how generate a customized PCIE interrupt from A10 FPGA to the Host, when my collection data is availabe ?

[JET60200]

hi everyone,

I'm using Arria10 device which is PCIe EP in x86 Host, i need to generate one customized PCIe interrupt when my collected data is full available, But I don't know How to implement it.

I had checked A10 pcie user guide, but is there any any design example for PCI express interrupt for my reference?

Thanks very much for any helps.

[SengKok_L_Intel]

Hi,

Are you using AVmm or AVst of PCIe IP?

Regards -SK Lim

[JET60200]

Hi,

I'm using avmm for A10 PCIe,

Best Regards

[SengKok_L_Intel]

For AVMM, you can use rxm_irq_<n> signals for interrupt request. What do you mean customize PCIe interrupt? Any difference with the standard one?

Regards -SK

[JET60200]

Thanks @SK,

My scenario is: when Arria10 received one wireless frame (data) of 1ms from the air attenna, I need trigger an (event) interrupt to notify x86 Host by using PCIe bus, that's what I mean " customize PCIe interrupt".

in your opinion, is there any Arria10 refrence design for this ？ ​

[SengKok_L_Intel]

You can create your logic to detect when the wireless frame is received, and then use the rxm_irq_i signal to trigger the interrupt. It should work.

Regards -SK

[JET60200]

Hi SK,

Our engineer checks our FPGA design, and found we use AVMM-DMA, instead of AVMM actually.

They said there's no " rxm_irq_i " pin line under AVMM-DMA mode. Is this correct ? AND if so, how to trigger the interupt undr AVMM-DMA on A10 pcie ?

Thanks for help.

[SengKok_L_Intel]

​For AVMM DMA, the DMA descriptor controller sends an MSI interrupt to the host via TXS interface. You need to enable export MSI interface to implement custom MSI interrupt handle and send the MSI interrupt via TXS interface, I apologize that there is no example for this as i can see.

Regards -SK

[william_tang]

Hi SK, I use Avalon-MM with DMA interface and export MSI/MSI-X conduit interfaces (In order to get the MSIIntfc_o[63:0]: MSI address and MSIIntfc_o[79:64]: MSI data). Then We write MSI data to MSI address by txs(Avalon Memory Mapped Slave) interface, can it generate a MSI interrupt?

[SengKok_L_Intel]

As far as I understand, you need to create a MSI (Memory Write) Transaction, and transmit through the TXS interface based on the information that you obtain from the MSI conduit interface,

Regards -SK