I keep getting following critcal warning for several projects:
Critical Warning (16562): Review the Power Analyzer report file (<design>.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures.
I have not found a proper way of getting rid of it, other than suppression. All our FPGA projects are automatically compiled and tested every night and every time changes are checked in. The build-server is set to fail builds with critical warnings, so we need to remove them. Only adding them to the .srf file seems like a "quick and dirty" workaround. Any better ways of dealing with this warning? Some way of "checking off" that the power report has been reviewed and is ok, rather than just ignoring the warning?
According to this KDB article, you can just ignore this assuming you are not exceeding the maximum power consumption of VCC_ONE:
So using message suppression is fine.
Thanks for reply.
I guess I had hoped for a way to "acknowledge" the power report rather than ignoring it, and have it re-generate based on some constraints, if something in changed.
Most of our designs will live for a long time (typ 10+ years of maintenance). There is no guarantee that the same designers are still here in 10 years, and it is not a given that someone new 10 years from now will understand why, or even notice that there is a critical warning being ignored.
With other critical warnings, e.g. timing - given proper constraints, if someone down the road does something "stupid", the build fails on "critical warning - timing not met", and whoever made the "stupid" change would have to deal with it right away, which is fairly easy since one would only need to analyze changes made during the last 24hr.