how to set timing constraint for jtag port

[lipingx]

[ak6dn]

See this post:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/altera-reserved-tck-in-timing-analysis-failure/m-p/1443221#M76635

[RichardTanSY_Intel · Accepted solution]

You may apply the SDC commands from this Intel® Quartus® Prime Timing Analyzer Cookbook User Guide:

https://www.intel.com/content/www/us/en/docs/programmable/683081/22-2/jtag-signals.html

Best Regards,

Richard Tan

[RichardTanSY_Intel]

May I know does my latest reply helps?

Best Regards,

Richard Tan

[lipingx]

yes, thanks

[RichardTanSY_Intel]

Thank you for acknowledge the solution provided. 

 I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you.

Best Regards,

Richard Tan

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