how to sync data out from dq_dqs in half_rate mode

[Altera_Forum]

hi,  

i am tring to design a custom DDR2 SO-DIMM controller in stratix iv gx device.   As the "External Memory Interface Handbook Volume 5" say, page 1-5, I need use that "half-rate resync_clk" from the I/O clock Divider to save the Read Data into one memory.  My problem is, the DQ bus is 64bits, and 4bits DQ will have one I/O clock divider, it will have total 64/4=16 half-rate resync_clk, Which one should i use?   thanks.