input[7..0] to output[0..7]

[Altera_Forum]

can i connect in .bdf file 2 bus in this mode? 

 input[7] -> output[0] input[6] ->output[1] ... input[0] ->output[7]     is this the right text mode?   input[7..0] output[0..7]

[Altera_Forum]

If, by text mode, you mean AHDL - then the answer is yes.

[Altera_Forum]

No, i do not want edit the verilog code. 

I want invert bus in bdf file

[Altera_Forum]

Connect input[7..0] and output[0..7] bus lines through a SOFT buffer

[Altera_Forum]

Tnk-you for reply, but i am a novice altera developer.. :( 

what is a SOFT buffer? regards

[Altera_Forum]

It is a virtual buffer that will be eliminated by logic synthesis. You find it in Primitives->Buffer section of bdf editor symbol libraries. 

Its purpose is only to allow you to connect traces with different names.

[Altera_Forum]

tnks . 

regards