input termination on ep4ce22f17c6(de0-nano terasic)

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

input termination on ep4ce22f17c6(de0-nano terasic)

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Hi! Can anybody explain how to enable input termination on ep4ce22f17c6(de0-nano terasic). I read quartus II handbook and cyclone IV handbook, but didn't find necessary information(may be read badly).

In .qsf I tried to write:

set_location_assignment PIN_A3 -to sdi_rx
set_instance_assignment -name IO_STANDARD LVDS -to sdi_rx
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sdi_rx

and had error

Error (169006): I/O pin "sdi_rx" specifies a Termination logic option setting of Differential, which is not supported by the device

May be ep4ce22f17c6 doesn't support input termination?

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