interface stratixIV with an external ultrafast comparator

[Altera_Forum]

Hi everybody :)  

 we need to interface ultrafast comparator- ADCMP572 - of analog device to a stratix4 device to perform one bit conversion. we expect that the comparator will ouput very short pulses(200 ps). The goal is to sample those pulses with FPGA. The comparator datasheet is attached  1) from a physical point of view, at which FPGA INPUT should we connect the output of the comparator -CML- in order that the short pulses can travel the FPGA with a minimum distortion ? must we connect to stratixIV transceiver only or can we to another inputs ?  2) we need to drive the LATCH differential input with a minimum jitter (<100ps) ? From which output of FPGA should we drive it ? must we connect to stratixIV transceiver only or can we to another inputs ?  Waiting for your response.. Shalom

[Altera_Forum]

You should make him think again. 

The idea is to keep the receiver in 'lock-to-reference' mode using the ATX PLL generated clock to shift in the data. In the Megawizard you set everything to 'bypass' and you will then get the 'raw' output of the deserialiser into the logic array. From there on starts your work interpreting the sampled data. You can use the Tx and Rx of the GT receivers separately (at least that is what I'm going to do in my Stratix II GX project). So you don't need to use the Tx part to sample your data on the Rx pins. Just make sure that the data is presented with the proper timing. Again you can simulate this with a small Quartus project.

[Altera_Forum]

Just for confirmation: We can use the GT receiver on FPGA to sample any asynchronous data ?

[Altera_Forum]

I tried it with a Stratix II GX at 5Gbps. The GX/GT blocks in Stratix IV are similar, so it should work. I would have tried it with Stratix IV but to simulate you need to use ModelSim and I haven't done that yet, I always use the Quartus internal simulator. 

In my simulation I may have been lucky to put the few bit values I tested in the right spot, but very probably you can sample any asynchronous data, just like FvM said.

[Altera_Forum]

I dont know if we do such thing here in the forum, but Its would be a big help, if you sent us your GT design code ;) 

 Shalom

[Altera_Forum]

You can have the .qar of the Stratix II GX project. Doing it for the Stratix IV GT is quite similar.

[Altera_Forum]

Big THANKS JosyB ! 

 You was a big help and a very good source of information !  Shalom

[Altera_Forum]

Shalom, 

 Reading back all the previous posts, I do agree Josyb about the following points:  1) You MUST use the GXB RX in “Lock To Reference” mode because your comparator output data being (roughly NRZ) random, there is no guarantee for the CDR unit to be able to properly recover the data (in other words: no embedded clock into the data).  2) You can bypass the PCS (RX PMA only) unless you have several comparators (multiple 1-Bit receivers) that need to be synchronized (in phased array application for instance). In that case, you can either use the word aligner + RX phase comp FIFO of the PCS or use a PMA-only channel with a synchronization state machine implemented in the FPGA fabric.  3) You’d better use an external dedicated clock generator to latch your comparator (Analog Device chip, Maxim, etc…). Stx Transceivers are targeted to high-speed digital data transmission and not clock generation. If your very first requirement is to achieve a low-jitter, do not use a GXB TX as a clock generator even if it’s look like a “charming” solution. Unless you have stringent cost reduction objectives, put an additional low-jitter programmable PLL device on your board.   Now, I have additional remarks:  Concerning the comparator/FPGA interface, I would add a high-speed DFF gate (ONsemi, Hittite, etc…) between the latch comparator and the Stx: In fact, when the Latch Enable input is HIGH, the comparator behaves like a basic analog comparator: it’s output may change accordingly to the random input signal. When LE input is LOW, the comparator stops comparing and hold the status of its output at the instant LE is switched LOW. That means The GXB RX have only a half clock period to properly sample the data. In adding an external DFF, it will have a full clock period to perform its job. When running @10 or 5 GHz, a clock period is short so a half period is very, very short… and I don’t speak about rise/fall times and jitter that reduce your valid time window.   Coupling between comparator/FPGA: the GXB RX need a common mode voltage of 0.82 or 1.1V. The ADCMP output Vcm is 2.2V (@Vcco=2.5V) è You will have to use AC-coupling: is it compatible with your requirements ?… Mind the behavior GXB RX Buffer if your comparator outputs a 000000… or 111111… pattern !  Finally, if you have to process the output of only a single 1-Bit receiver, why do you target a Stx IV device ? To demultiplex the high-speed bit rate, you could implement an external demux device as well (Maxim MAX3950 or Inphi 1385-DX) and process the demultiplexed data in a cheaper and less complex device.

[Altera_Forum]

Hi OliB 

 Desole du retard... Thanks for those explanation. They are very useful and interesant. First, the choice of target Stx IV comes from others reasons, not necessarily technical. 1)We are interested on a 8Gbps operation transceiver, so from StxIV datasheet we need to use 0.82V for VCM at the receiver.. 2)we would like to focus on the "coupling between comparator/FPGA": From stratixIV datasheet, we understand that the "Absolute VMIN for a receiver pin" (Transceiver input) is (-0.4V) and the "Absolute VMAX for a receiver pin" is 1.6V. So we cannot directly drive the StxIV transceiver input by the comparator output, its rigth? Using AC coupling cannot support 8Gbps operation, rigth ?  Shalom

[Altera_Forum]

OliB revealed, that ADCMP572 uses a different flavour of CML than Stratix IV, that can't be DC coupled to each other directly. I understand, that the signal nature doesn't allow AC coupling in this case. So some kind of DC level shift is required.

[Altera_Forum]

So, it seems that the only solution for that, is an external cicuitry.