Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20826 Discussions

issue with IOPLL in quartus prime 18.0

Matt1
Beginner
1,917 Views

error reported as

Error(19252): None of the output clocks of IOPLL "pll_test|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst" are connected. Please use at least one

All the pins in the PLL components are connected properly and never faced such issues in the previous megafunction.

can somebody suggest a solution

0 Kudos
5 Replies
a_x_h_75
New Contributor III
1,656 Views

I suspect Quartus is removing any logic that you are driving from your PLL clock output signal. It will do this if no output pins on the device depend on that logic.

 

Make sure at least one FPGA pin is driven from the logic that is clocked from the PLL to ensure it's not removed by Quartus.

 

Cheers,

Alex

0 Kudos
Matt1
Beginner
1,656 Views

thanks Alex,

i think you are right.

Actually I assigned one of the output to a signal so that it can be connected to a different module.

thanks for the help.

 

0 Kudos
Rahul_S_Intel1
Employee
1,656 Views

Hi Matt,

The above issue is due to the quartus optimization of the logic, make sure that when using the ip to connect to the logics

0 Kudos
Matt1
Beginner
1,656 Views

thanks RSree for your reply.

I want to keep the component in my design and i dont want to connect to any logic,(that is,connect the output to a signal)

I hope it was possible in megafunction.

can you suggest some possibility.

0 Kudos
Rahul_S_Intel1
Employee
1,656 Views

From the above discussion,I assume the quartus is optimizing the logic /IP . if that is the case , I am requesting to enable

The below options from assignment editor.

 

Preserver Fan-out Free Register Node :Yes

Netlist Optimization : Never Allow

Preserve Registers : Yes

 

 

0 Kudos
Reply