Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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making a processor

Altera_Forum
Honored Contributor II
‎04-28-2011 06:01 PM
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I am currently working on a processibng machine that will be programmed onto an altera fpga cyclone 2. I have completed the code and found an interesting issue. it is a 16 bit input and output. i can subtract 1 1 1 1 from 5 5 5 5 and get 4 4 4 4 but i cant subtract 1 1 1 1 from 0 0 0 0 and get F F F F here is the code:

i have omitted the clock debouncing modules

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Altera_Forum
Honored Contributor II
‎04-29-2011 12:19 AM
369 Views

 

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i can subtract 1 1 1 1 from 5 5 5 5 and get 4 4 4 4 but i cant subtract 1 1 1 1 from 0 0 0 0 and get F F F F 

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Maybe that is because 0000 minus 1111 equals EEEF not FFFF. 0000 - 0001 would be FFFF.
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