Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21611 Discussions

max speed for banks (MAX10)

Altera_Forum
Honored Contributor II
‎09-19-2016 07:42 AM
1,298 Views

Hi Community, 

 

i looked up different datasheets but didn't found the information about the speed for the single banks. 

It is written in quartus that the banks 1 & 8 have lower speed than the rest of them. 

But what is the difference in speed? 

Where can I find this information? 

 

I'll only use the FPGA for LVCMOS logic.  

Where can I find the option to pick the I/O standard LVCMOS 2.5V in the Pin Planner. It only shows the 3V and 3.3V option. Do I have to use 2.5V default? 

LVDS won't be used and the imigration of a DDR3 interface is planned for the far future, but not needed at this time. 

 

So, could you please tell me where to find the speed information? 

Or what is the low speed rate and what the high speed rate? 

What is the amount of difference? 

 

Thanks in advance. 

Jérôme
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎09-19-2016 03:01 PM
422 Views

You won't find a maximum speed for an I/O pin. It varies based on what is connected to it. You will need to compute it based on the impedance of the transmission line the output is driving. I've not done such a calculation so I can't help with it.

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.