Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20678 Discussions

maximum IOs per bank

Altera_Forum
Honored Contributor II
‎09-20-2016 08:56 AM
815 Views

Hi Community, 

 

referred to the m10_sidg.pdf p.7 table 2. I will use a deserializer (MAX9276) and the outputs of this IC are using the LVCMOS standard. 

I looked up the DS of the IC with the electrical characteristics and under my given input signals (RX TX), there is an output current of 3mA. 

Does this mean I can only use 65% of each bank, because it is not recommended to use more than 65% of each bank using the I/O Standard? 

 

Regards 

Jérôme
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.