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Hello.
I am a new to vhdl and as a part of my tranning i need to multiplay 2 numbers can u help me and tell my what i doing wrong? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; ENTITY MUL IS PORT( a,b: IN unsigned (3 downto 0); y : OUT unsigned (7 downto 0)); END MUL ; ARCHITECTURE Behavioral OF MUL IS BEGIN process (a,b) variable temp1:unsigned(7 downto 0); variable temp:unsigned(7 downto 0); BEGIN for j in 0 to 3 loop if (b(j)='0') then temp1:=(7 downto 0 =>'0'); else temp1:=( j=>a(0),j+1=>a(1), j+2=>a(2),j+3=>a(3),others=>'0') ; temp:=temp+temp1; end if ; end loop; y<=temp; end process; END Behavioral;Link Copied
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whats wrong with
y <= a*b; But if you need to build your own multuplier - you havent said what problems you are having with this code.- Mark as New
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Yes i need to built my own multiplier my problem with the code is that logically i think it is ok and also compile but when i enter signals i am getting that y(out) is in unknown state..
Thx.- Mark as New
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That means temp is unknown and probably temp1 aswell
Get a good testbench going in modelsim. This is debugging that you need to do yourself.- Mark as New
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I am using a wrap program and active vhdl sim. so i dont need test banch can u see the code and maybe guide me why temp1 and temp getting an unknown state?
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because temp is never initialised.
And 'U' is not unknown, it is uninitialised. 'X' is unknown- Mark as New
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Ok thx i will try to fix it thx.
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I tried today this was not the issue but still thx .
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--- Quote Start --- I tried today this was not the issue but still thx . --- Quote End --- Are you referring to your original code? With Quartus synthesis, the missing initialization of temp is exactly the issue.

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