Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21607 Discussions

nStatus can't go high

Altera_Forum
Honored Contributor II
3,711 Views

I have just finished my pcb of EP3C25F324, but it can't work 

when I power on the board, all user IO pins stayed high, the nSTATUS remaid low, and nCONFIG statyed high. Is't the problem of POR? Or the power of VCCA,VCCINT,VCCIO have some problem? 

I used the JTAG an AS config way via the Figure 10-30 on cyclone3 device handbook,following is my scheme,and I connect VCCIO1 to the VCC3.3,and the others to the VCC2.5. 

http://1824.img.pp.sohu.com.cn/images/2009/6/17/9/26/122983f4b5dg214.jpg
0 Kudos
15 Replies
Altera_Forum
Honored Contributor II
2,096 Views

So are you able to program something into the EPCS flash? Are you able to program the part via JTAG? 

 

Jake
0 Kudos
Altera_Forum
Honored Contributor II
2,096 Views

thanks for your reply! 

I can't program anything via JTAG,when I config the FPGA ,the quartus programmer said:can't access the JTAG(I use usb blaster).
0 Kudos
Altera_Forum
Honored Contributor II
2,096 Views

Can you list what all of your voltage rails are connected to including VCCINT? 

 

Jake
0 Kudos
Altera_Forum
Honored Contributor II
2,096 Views
0 Kudos
Altera_Forum
Honored Contributor II
2,096 Views

Since nSTATUS is stuck low it sounds like it could be a POR problem. Though I don't know of a POR problem with this specific device for Altera. But there are other reasons a device may not exit POR too, like voltage levels on supplies all must be above the POR trip points, control pins need to be tied or driven correctly, etc...  

 

Debug techniques:  

 

I would put a scope on nSTATUS and trigger on a rising edge, single sequence (Single event trigger, one time trigger). Try varying trigger point voltage levels. Around 0.2 to 0.8V and look for a rising pulse then nSTATUS should drive low when entering POR, but should also release nSTATUS back high again after POR. 

 

Also list for us your voltage supplies and what they are powered to. Especially VCCIO of the banks that have configuration pins in them. I noticed the JTAG header is powered at 2.5V, the EPC is powered at 3.3V, what are the voltages of VCCIO for these banks?
0 Kudos
Altera_Forum
Honored Contributor II
2,096 Views

thanks for your help,I will try the Debug techniques later. 

as the scheme of powet above, I connect the VCCIO of bank1 to the 3.3V, 

I have doubt this, because the jtag pins and EPC pins are both in the bank1, but jtag is powered at 2.5V and EPC is powered at 3.3V.  

I followed the Figure 10-30 on cyclone3 device handbook to design the config scheme(Programming Serial Configuration Devices In-System Using the JTAG Interface). 

 

VCCIO of bank1: 3.3V 

VCCIO of other banks: 2.5V 

VCCINT:1.2V 

VCCA: 2.5V 

MSEL :0010 (1 to 2.5V) 

(you can see the detailed connection via the scheme above, maybe it's not clear enough, you can save it to your local coputer and then enlarge it)
0 Kudos
Altera_Forum
Honored Contributor II
2,096 Views

Just following up to see if you managed to resolve the problem, need more help, moved on to other things, etc... ???  

 

If you resolved it... what did you determine the root cause of the problem to be? What was your resolution?
0 Kudos
Altera_Forum
Honored Contributor II
2,096 Views

Hi, 

I have the same problem. My device is EP3C55F484. I'm using JTAG and SFL to programm my EPCS16. All VCCIOs are 3.3V, VCCINT = 1.2V, VCCD_PLLs are 1.2V and VCCA = 2.5V. JTAG is powered by VCCA, TDI and TMS are tied to VCCA via 1k, TCK is tied to GND via 1k. MSEL: 0010. 

 

When I power on my board nSTATUS stays low, nCONFIG stays high. I doublechecked all voltage levels and everythig was fine. I think that Cyclone can't exit POR but I don't understand why((
0 Kudos
Altera_Forum
Honored Contributor II
2,096 Views

I met the same problem with you: the nstatus can not go high and I can't configured the EP3C40 via JTAG neither.  

 

So have anyone solved this problem? Maybe you can help me with your experience. 

 

Many thanks.
0 Kudos
Altera_Forum
Honored Contributor II
2,096 Views

I have solved the JTAG problem. The reason is that VCCINT and VCCA were not powered correctly. 

 

 

--- Quote Start ---  

I met the same problem with you: the nstatus can not go high and I can't configured the EP3C40 via JTAG neither.  

 

So have anyone solved this problem? Maybe you can help me with your experience. 

 

Many thanks. 

--- Quote End ---  

0 Kudos
Altera_Forum
Honored Contributor II
2,096 Views

 

--- Quote Start ---  

I have solved the JTAG problem. The reason is that VCCINT and VCCA were not powered correctly. 

--- Quote End ---  

 

 

can you show me more details? thank you!
0 Kudos
Altera_Forum
Honored Contributor II
2,096 Views

can you show me more details? 

 

I have some problem. 

Where i made mistake? 

 

Cyclone 4: EP4CE6E22C8n 

 

VCCINT: 1.2V 

VCCA: 2.5V 

VCCD_PLL: 1.2V
0 Kudos
Altera_Forum
Honored Contributor II
2,096 Views

Could you help me?

0 Kudos
Altera_Forum
Honored Contributor II
2,096 Views

I have solved problem. No pad on board for e-pad of cyc4 E package. 

Resolder Cyc4, and connect e-pad via wire.
0 Kudos
Altera_Forum
Honored Contributor II
2,096 Views

I met the same problem with you: the nstatus can not go high and I can't configured the EP4CE22 via JTAG neither.  

 

So have anyone solved this problem? Maybe you can help me with your experience. 

 

FPGA: CYCLONE IV E EP4CE22E22C8 

Quartus II version: 15.1 

Document referred: cyclone IV E handbook page number : 8-56 and figure 

Figure 8–29. Programming Serial Configuration Devices In-System Using the JTAG Interface 

 

Customer made three protoboard , I am testing /working on two protoboard. 

· First protoboard : using JTAG mode, device detected and programming process 100%. 

· Issue during programming of a serial configuration device with the JTAG interface through the SFL : EPCQ device detected, programming of EPCQ done, but configuration data not transferred from EPCQ to FPGA after power up and nstatus pin remain low. 

Here I am explaning you the procedure which I followed. 

1) Checked all voltage supply at output of board’s regulators  

VCCINT = 1.170 

VCCD_PLL=1.189 

VCCIO= 3.3 

VCCA = 2.5 

 

2) Checked all JTAG voltage at male header side. 

TCK = GND. 

TMS = 2.142. 

TDI = 2.142. 

TDO = floating. 

VCCA = 2.5V 

 

3) Checked MSEL pin as follow (cyclone IV E handbook page no. 173) 

MSEL[0] = 3.3V 

MSEL[1] = 0V 

MSEL[2] = 3.3  

 

4) Checked all Resistor value. 

 

5) Document refer: As I mentioned above. 

 

6) nCE pin : GND 

 

7) nCEO: NC 

 

8) nstatus : After the power up , this pin remain low for both the proto board: 

 

1) First proto board, nstatus = 0.502V , device detected thru programmer but EPCQ to FPGA configure data not transferred. means configuration error 

2) Second proto board, nstatus = 0.054v device does not detected. 

 

9) Nconfig : After the power up , this pin remain high for both the proto board, voltage level as below. 

1) First proto board (device detected board) = 3.3V 

2) Second proto board (device did not detect board) = 2.730 

 

10) CONF_DONE : After power up, CONF_DONE pin remain low. 

 

11) EPCQ device connection with FPGA. 

 

1) DATA[0] pin of FPGA to DATA pin of EPCQ. 

2) DCLK pin of FPGA to DCLK pin of EPCQ. 

3) nCSO pin of FPGA to nCS pin of EPCQ. 

4) ASDO pin of FPGA to ASDI pin of EPCQ. 

 

 

RAHUL SONI
0 Kudos
Reply