Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

pll simulation

Altera_Forum
Honored Contributor II
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Hello, 

I have to use a pll in my design. so I've created a pll via megawizard with my needs. 100Mhz clock input and 5nsec shifted clock in the output. 

 

now, I want to simulate my design with modelsim. how can I do that? 

where should I place the PLL.vhd component, I put it inside top.vhd and i am getting errors "Unknown identifier" to all pll I/Os. 

 

can you assist?
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Altera_Forum
Honored Contributor II
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Hello, 

 

Wrap it inside an entity that is then instantiated in your testbench. Keeps the same entity as top in Quartus. 

 

Don't know how correct it is - but it works for me :) 

 

 

M.
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Altera_Forum
Honored Contributor II
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My design hierarchy is : TestBench -->top level-->Pll 

 

did you do the same?
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Altera_Forum
Honored Contributor II
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Yeah, pretty much. Modelsim needs an altera library to simulate their things tho, altera_mf if I remember correctly. When defining you pll in the megawizard you need to check off that one also.

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Altera_Forum
Honored Contributor II
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It works, 

Thanks!!!:)
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