porting code from SRAM to SSRAM, bursting confusion

[Altera_Forum]

Hi all, 

 I'm trying to port some code which used an SRAM chip on a DE1 board, to use the SSRAM chip on a DE2-70 board.  My main concern and confusion is the fact that SSRAM uses bursting. The code which used the DE1 SRAM, supplied "random" addresses constantly to the controller every clock cycle, and expected valid data after a 3 clock cycle delay (input and output ports were registered), effectively pipelining the read transfers with just 1 clock delay.  Now, my question: Is it possible to supply "random" addresses every clock cycle aswell to the SSRAM controller, without using the bursting feature, ie. always do a single read, and expect data with a 3 clock cycle pipeline delay?   Reading some information about the workings of an SSRAM seem to suggest that a single read must be completed first, before new addresses can be supplied. This is why bursting was invented - this would be very bad, as this would not allow pipelining of random address reads.  Can anyone shed some light on this? Thanks.

[Altera_Forum]

Read from arbitary addresses can be performed with SSRAM @CLK/2 throughput while burst read achieves full CLK speed. So you have to use a double clock speed for the SSRAM related to your data clock. This shouldn't be an issue, considering it's timing specification. The design complexity increases, however.

[Altera_Forum]

I've done some testing, and the SSRAM chip I am using is capable of pipelining arbitrary addresses for reads. Just thought to clear it up.

[Altera_Forum]

What part number is the SSRAM are you using?

[Altera_Forum]

The part number is IS61LPS51236A, it came with the DE2-70 board from terasic.

[Altera_Forum]

kwuaker, 

There is an ip core for SSRAM (on DE2-70) in university ip library. I am a beginner and haven't get it work yet. I attach the file. It may be useful for you.

[Altera_Forum]

I've made my own controller based on that one. That controller does not allow arbitrary reads for one simple reason: it deselects the chip select while it is waiting for data to return. To make it work, simply assign the chipselect signal to the 3 SSRAM chipselects. 

 Though, the controller should work if you're using it only with the nios cpu. Why didn't it work for you?

[Altera_Forum]

--- Quote Start ---  I've done some testing, and the SSRAM chip I am using is capable of pipelining arbitrary addresses for reads. Just thought to clear it up.  --- Quote End ---    Indeed, and as a matter of fact, some SSRAM datasheets show waveforms for back-to-back reads without bursting.  The question is then, why those chips has special support for bursting? Unless I miss something, you don't gain anything at all by using the ADV pin and the SSRAM internal burst counter.  Special bursting makes sense on RAM parts with multiplexed row and column lines. But here there is no such multiplexing, so I don't see what is the purpose of bursting.  Anybody?

[Altera_Forum]

I don't see any gain either. I guess it's there to make the SSRAM more compatible with processors that use bursts.

[Altera_Forum]

Seems the reasons are related to the original purpose of this type of SSRAM. This RAM was designed to be used mainly as CPU cache, where the RAM control was shared between the CPU and the memory controller.

[Altera_Forum]

--- Quote Start ---  I've done some testing, and the SSRAM chip I am using is capable of pipelining arbitrary addresses for reads. Just thought to clear it up.  --- Quote End ---     Hi kwuaker,   It seems this is too old post, but let try.^^.  Could you please show me how to control SSRAM to read pipeline arbitrary addresses ? I did tie 3 SSRAM chipselects fixed values (CS_N1, CS_N3 = 1'b0; CS_2 = 1'b1), but it still can not read pipeline, "a single read must be completed first, before new addresses can be supplied" as you mentioned.   Khai,

[Altera_Forum]

assign SRAM_ADSP_N = ~(is_read); 

assign SRAM_CE1_N = 1'b0; assign SRAM_CE2 = 1'b1; assign SRAM_CE3_N = 1'b0;   By above modifications, the read pipeline arbitrary addresses with one latency cycle can be achieved.^^.