problem with adaptive FIR ,i realy need your help

Altera_Forum · ‎03-03-2014

hi all guys,i'm freshmem in forum,i got a problem with my vhdl code about adaptive FIR filter.I try write by myself but it fail (simulate in modelsim-altera),so that i write agian based on "dsp with fpga" but i found the error in that code


library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity ab is
 port ( xin :in std_logic_vector(7 downto 0);
        clk: in std_logic;
		  y :out std_logic_vector(7 downto 0);
		  y1 : out std_logic_vector(7 downto 0));
end ab;
architecture Behavioral of ab is
subtype n1bit is std_logic_vector(7 downto 0);
type array_n1bit is array(0 to 2) of n1bit;
signal x : array_n1bit;
signal f : array_n1bit :=((others=> (others=>'0')));
begin
 process
 begin
 wait until clk='1';
 x(0)<=xin;
 x(1)<=xin;
 f(0)<=f(0)+x(0);
 --f(1)<=f(1)+x(1);
 end process;
 y<=f(0);
 y1<=f(1);
end Behavioral;

i separate the orignal code and found that error is about f(1),f(0) but i don't know how to solve this situation(i had complie but there are no errors, when testbench waveform the output alaways xxxxxx......) ,please hepl me,thanks

Altera_Forum · ‎03-03-2014

I'm not sure how the code is related to "adaptive FIR", but there are no syntax errors.

Altera_Forum · ‎03-04-2014

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I'm not sure how the code is related to "adaptive FIR", but there are no syntax errors.

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yeah,but when i simulate ,it's wrong,the output just xxxxxxxxx.....

Altera_Forum · ‎03-04-2014

O.K., I see, but it's a pure functional simulation problem.

In first clock cycle, uninitialized x(0) and x(1) are added to f(0) and f(1). You easily find the problem looking at all design nodes in simulation, not just the output.

You had saved your and my time by giving a clear problem description in your first post.

Altera_Forum · ‎03-04-2014

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O.K., I see, but it's a pure functional simulation problem.

In first clock cycle, uninitialized x(0) and x(1) are added to f(0) and f(1). You easily find the problem looking at all design nodes in simulation, not just the output.

You had saved your and my time by giving a clear problem description in your first post.

--- Quote End ---

yeah,but how to solve this sitiation,here is totally code


----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_signed.all;
entity firlms is
generic(W1: integer :=8;
        W2: integer :=16;
		  L: integer :=2);
port ( clk : in std_logic;
       x_in: in std_logic_vector(W1-1 downto 0);
		 d_in: in std_logic_vector(W1-1 downto 0);
		 y_in : in std_logic_vector(W2-1 downto 0);
		 e_out,y_out,e1,y1:out std_logic_vector(W2-1 downto 0));	  
end firlms;
architecture Behavioral of firlms is
component mult 
 port ( dataa : in std_logic_vector(7 downto 0);
        datab : in std_logic_vector(7 downto 0);
		  result : out std_logic_vector(15 downto 0));
end component;
subtype n1bit is std_logic_vector(W1-1 downto 0);
subtype n2bit is std_logic_vector(W2-1 downto 0);
type array_n1bit is array(0 to L-1) of n1bit;
type array_n2bit is array(0 to L-1) of n2bit;
signal d,k :n1bit;
signal emu : n1bit;
signal y,sxty:n2bit;
signal e,sxtd:n2bit;
signal x: array_n1bit;
signal f : array_n1bit :=((others=> (others=>'0')));
signal p,xemu:array_n2bit;
begin
dsxt:process(d)
 begin
  sxtd(7 downto 0)<=d;
	for k in 15 downto 8 loop
	sxtd(k)<=d(d'high);
	end loop;
 end process;
 store:process
  begin
   wait until clk='1';
	--y <= y_in;
	d <= d_in;
	x(0) <= x_in;
	x(1) <= x(0);
	f(0)<=f(0)+xemu(0)(15 downto 8);
	f(1)<=f(1) +xemu(1)(15 downto 8);
  end process store;
--y<=p(0)+p(1);
ysxt:process(y)
 begin
  sxty(8 downto 0)<=y(15 downto 7);
   for k in 15 downto 9 loop
	 sxty(k)<=y(y'high);
	end loop;
 end process;
 e<=sxtd-sxty;
 emu<=e(8 downto 1);
 mulgen2:for i in 0 to L-1 generate
 fir: mult port map (dataa=>x(i),datab=>emu,result=>xemu(i));
 end generate;
 --y_out<="00000000"&xemu(1);
 --e_out<="00000000"&xemu(0);
 e1<="00000000"&f(1);
 y1<="00000000"&f(0);
end Behavioral;
-------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity mult is
 port ( dataa : in std_logic_vector(7 downto 0);
        datab : in std_logic_vector(7 downto 0);
		  result : out std_logic_vector(15 downto 0));
end mult;
architecture fpga of mult is
begin
result<=dataa*datab;
end fpga;
-----------------------------------------------------------------------------------------------------------------

Altera_Forum · ‎03-04-2014

It is easily fixed - just give X(0) and (1) an initial value.

signal x : array_n1bit := (others => (others => '0'));

Altera_Forum · ‎03-04-2014

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It is easily fixed - just give X(0) and (1) an initial value.

signal x : array_n1bit := (others => (others => '0'));

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can you show me your wave form ,i'm not next to my computer

Altera_Forum · ‎03-04-2014

I havent made a wave form - thats your job...

Altera_Forum · ‎03-04-2014

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I havent made a wave form - thats your job...

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it work!!!!!!!!!!!!!!!!!!!!!! thanks so much

Altera_Forum · ‎11-15-2017

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it work!!!!!!!!!!!!!!!!!!!!!! thanks so much

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Hello, can you share the code please ? i'm trying to use it on a nexys 4 ddr. thank you