problems with SERDES

[Altera_Forum]

hellow, 

 We have to transmit a pulse to a laser, this pulse is between 0.2 and 1µs. and a duty cycle between 50 and 100ns.   This signal we have to 'catch', herefor we will use the high speed input of the serdes (receive).   We've read that it is normal to use clock recovery, but we don't need it. So it is possible to switch it off or are there other solutions?   Best regards

[Altera_Forum]

You might want to peruse this thread (http://www.alteraforum.com/forum/showthread.php?t=23214&page=4) first. It discusses a similar setup.

[Altera_Forum]

What are the properties of the pulse you care about? 

 If you only care that the pulse 'occurred' you could simply use it as a clock signal to a register. That register can toggle a signal each time a pulse is received. The toggling signal can then be synchronized to an FPGA clock, and a pulse in that domain used to set a flag, start/stop counters etc.  If you need to know how long the pulse was asserted for, then you basically want a 1-bit ADC, i.e., the SERDES channel. What type of accuracy do you need the pulse time to be measured?  You can use the ALTGX function without having to perform clock and data recovery. You could also use an ALTLVDS component up to about 1Gbps sampling frequency (1ns).  The implementation you need depends on what you are trying to measure, and what FPGA family you are planning to use. Could you please clarify.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  What are the properties of the pulse you care about?   If you only care that the pulse 'occurred' you could simply use it as a clock signal to a register. That register can toggle a signal each time a pulse is received. The toggling signal can then be synchronized to an FPGA clock, and a pulse in that domain used to set a flag, start/stop counters etc.   If you need to know how long the pulse was asserted for, then you basically want a 1-bit ADC, i.e., the SERDES channel. What type of accuracy do you need the pulse time to be measured?   You can use the ALTGX function without having to perform clock and data recovery. You could also use an ALTLVDS component up to about 1Gbps sampling frequency (1ns).   The implementation you need depends on what you are trying to measure, and what FPGA family you are planning to use. Could you please clarify.   Cheers, Dave  --- Quote End ---     Hello Dave,   we would work with the Stratix GX. This is the first time we are going to work with the SERDES, so we're still looking for information because we find it difficult to understand... And it's been a while that we worked with vhdl..   Greetings

[Altera_Forum]

You didn't mention any timing requirements yet, besides saying that you want to catch a pulse. I think, it doesn't mecessarily involve measuring an exact pulse width. So how about some clarification?

[Altera_Forum]

--- Quote Start ---  You didn't mention any timing requirements yet, besides saying that you want to catch a pulse. I think, it doesn't mecessarily involve measuring an exact pulse width. So how about some clarification?  --- Quote End ---     We sent a pulse from 50 to 100ns duty cycle and 0.2-1µs period, and this puls we want to catch with a photodetector.  We want to use the SERDES because we want to read the signals in very fast. It is for a detection system...   Greetings

[Altera_Forum]

--- Quote Start ---  We want to use the SERDES because we want to read the signals in very fast.  --- Quote End ---   Yes, that's been said. I thought about hearing a speed number.

[Altera_Forum]

Hi Mathais, 

 You have told us what the pulse looks like, but you have not told us what you want to know about it.  What does 'catch' mean to you? What do you want to do every time you 'catch' the pulse?  Do you want to gather statistics on the pulse high-time, low-time, do you want to average pulses together, etc?  Pulse widths of 50ns to 100ns can be used to clock regular I/O on an FPGA, or you can capture more detail about the pulse using the SERDES or an ALTLVDS transceiver channel.  If you could explain things at more of a system-level, then we can suggest an implementation.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  You might want to peruse this thread (http://www.alteraforum.com/forum/showthread.php?t=23214&page=4) first. It discusses a similar setup.  --- Quote End ---   Mathias, did you read that post? Anyway, you can use the generated PLL clock in stead of the CDR-clock in Stratix II (and up) Serdes by setting the lock_to_reference bit. You can feed the photodetector input into the RX-pin of the FPGA and get up to 160 ps resolution. I have no idea how accurate the bit-sampling will be as the input signal is totally asynchronous to the Serdes receiver clock (meta-stability issues?). I suspect you are setting up a LIDAR-like system?