problems with passive serial configuration of EP4CGX150DF31C8N from host processor

[CNash2]

get multiple nstatus assertions. at consistent point during configuration cycle

q v17 and v15 used with and without compression

schematic as per handbook

msel3-0 = 1000

[ShafiqY_Intel]

Hi CNash2,

When you want to program the design into CFI flash, Make sure you tick only on "your design". do not tick the bit_option

For more details, maybe you can refer to forum below. I answered to the user there.

https://forums.intel.com/s/question/0D70P000006Qq88/problem-configuring-cyclone-10-lp-in-passive-serial-mode?s1oid=00DU0000000YT3c&s1nid=0DB0P000000U1Hq&emkind=chatterCommentNotification&s1uid=0050P000008IfUR&emtm=1563549800416&fromEmail=1&s1ext=0

Cheers.

[CNash2]

many thanks