I want to generate 25Hz,50Hz,100Hz pulse signals!The singal is bad when I use frequency division! Is there a better way to generate the signals? Thank you very much! --a friend from China!
--- Quote Start --- Why the signal is bad with frequency division? Do you use schematic or HDL code? --- Quote End --- i use verilog ,the square wave contains lots of high frequency waves! i also use PLL!
Do you see the high frequency glitches experimentally?If yes, did your logic analyzer sample your output synchronously? If not sampling synchronously, it is normal that you see glitches. Remember that you only need that the outputs are stable and have the proper values one setup time before the next active clock edge.