Re: quartus doesn't show connection in state machine

Altera_Forum · ‎11-25-2010

Hi there,

I have problem with my project, excatly with state machine.

Quartus compiles code atached below with no errors, but in state machine viewer i can see only states without connections between them.

What's wrong with project?

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
ENTITY stateMachine IS
port(
    clk : IN std_logic;
    rst : IN std_logic;
    
    indicator_1_0 : IN std_logic_vector(1 downto 0);    
    ena_init : OUT std_logic;
    release_register : OUT std_logic;
    release_result : OUT std_logic;
    set_to_zero_1 : IN std_logic;
--    set_to_zero_2 : IN std_logic;
    ena_1 : OUT std_logic;
    ena_2 : OUT std_logic
);
END stateMachine;
ARCHITECTURE stateMachineArch OF stateMachine IS
TYPE state_t IS (idle, P1, P2, memory_init, load, inter);
SIGNAL curState, nextState : state_t;
BEGIN
automatStanow : process (clk, rst, indicator_1_0, set_to_zero_1, curState)
VARIABLE initialisationCounter : INTEGER;
BEGIN
CASE curState IS
    WHEN idle =>
    ena_1 <= '0';
    ena_2 <= '0';
    release_register <= '0';
    release_result <= '0';
    ena_init <=  '0';
    IF (indicator_1_0 = "11") THEN
        nextState <= P1;
    ELSE
        nextState <= idle;
    END IF;
    WHEN P1 =>
    ena_1 <= '0';
    ena_2 <= '0';
    release_register <= '0';
    release_result <= '0';
    ena_init <=  '0';
    IF (indicator_1_0 = "00") THEN
        nextState <= P2;
    ELSE
        nextState <= idle;
    END IF;
    WHEN P2 =>
    ena_1 <= '0';
    ena_2 <= '0';
    release_register <= '0';
    release_result <= '0';
    ena_init <=  '1';
    initialisationCounter := 0;
    WHEN memory_init =>
    ena_1 <= '0';
    ena_2 <= '0';
    release_register <= '0';
    release_result <= '0';
    ena_init <=  '1';
    initialisationCounter := initialisationCounter + 1;
    IF (initialisationCounter = 3072) THEN
        nextState <= load;
    ELSE
        nextState <= memory_init;
    END IF;
    WHEN load =>
    ena_1 <= '1';
    ena_2 <= '0';
    release_register <= '0';
    release_result <= '0';
    ena_init <=  '0';
    initialisationCounter :=0;
    IF (set_to_zero_1 = '1') THEN
        nextState <= inter;
    ELSE
        nextState <= load;
    END IF;
    WHEN inter =>
    ena_1 <= '0';
    ena_2 <= '1';
    release_register <= '1';
    release_result <= '1';
    ena_init <=  '0';
    IF (indicator_1_0 = "11") THEN
        nextState <= P1;
    ELSE
        nextState <= idle;
    END IF;
END CASE;
END PROCESS;
zamianaStanow: PROCESS(clk, rst)
    BEGIN
        IF (rst = '1') THEN
            curState <= idle;
        ELSIF (rising_edge(clk)) THEN
            curState <= nextState;
        END IF;
    END PROCESS;
END stateMachineArch;

Altera_Forum · ‎11-25-2010

One of your states (state P2 to be precise) doesn't have an assignment for nextState, and the compiler infers latches for all states.

You should always check for 'inferred latches' in the message panel and repair the cause. I don't know of any valid use for 'latches' in user code, although some experts may differ.

Altera_Forum · ‎11-25-2010

Thanks a lot! It helps.