Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21615 Discussions

questasim schematic painfully slow

erik_ski
Beginner
337 Views

Hi everyone, 

me and my colleagues are having trouble using questasim's schematic view. It becomes extremely slow (~0.2 fps or 5 seconds per frame) , a bit faster with extremely simple designs like an adder, but still not usable. We have tested questa 21, 24 on ubuntu 22 , 24 and centOS stream 10. It looks like something too big for not seeing any similar questions on the internet, which I didn't, so I'm guessing there is something wrong with the configuration. 

We're using the free license.

 

Thank you in advance! 

0 Kudos
5 Replies
RichardTanSY_Altera
279 Views

I would suggest using the Quartus RTL Viewer instead to check the schematic view.

We primarily use Questa Altera FPGA Edition for simulation purposes, but not much for viewing schematics.

Also, which Questa FPGA Edition are you currently using?


Regards,

Richard Tan


0 Kudos
erik_ski
Beginner
244 Views

Thank you. I'm using FPGA Starter Edition 2024.3. It has surprised me that the compatible OSes are only redhat 8 https://www.intel.la/content/www/xl/es/support/programmable/support-resources/design-software/os-support.html

Do you think a different license could make a difference? 


 

Best regards,
Erik

0 Kudos
sstrell
Honored Contributor III
200 Views

As stated, a simulation tool is not really the thing to use for looking at a design schematic.  Any reason why you're using it this way instead of just using the RTL viewer in Quartus?

0 Kudos
RichardTanSY_Altera
68 Views

Changing the license is unlikely to affect the results, but you may still give it a try if you'd like to rule it out.

For viewing the schematic, I recommend using the RTL Viewer available in Quartus Prime.

You can refer to the documentation here:

https://www.intel.com/content/www/us/en/docs/programmable/683230/18-1/rtl-viewer-overview.html


Regards,

Richard Tan


0 Kudos
RichardTanSY_Altera
32 Views

Hi,

 

Please be informed that starting October 1st, the FPGA Forum on community.intel.com will be placed in read-only mode.

You will still be able to view and access existing content, but new posts, comments, or edits will no longer be permitted during this transition period.

For urgent technical support, we kindly ask that you reach out through Intel Premier Support (IPS) via your DFAE (Altera authorised distributors) engagement.

We appreciate your patience as we prepare for the official launch of the new FPGA forum on October 14th, where posting capabilities will resume.

 

Thank you for your continued support and understanding.

 

Regards,

Richard Tan

 

0 Kudos
Reply