question about SRAM and DRAM on FPGA chip

[Altera_Forum]

Hi All, 

  I am currently working on DE4 and I wanna to figure out how many clock cycle and the latency that SRAM(in stratix IV chip) take when it performs read and write operations. Moreover, I wanna learn more about the DRAM on the board,such as latency etc. Unfortunately, I didnt find them in Stratix IV Device handbook, can anyone she some light on it?Thanks.

[Altera_Forum]

INternal RAM does everything in a single clock cycle. You find the basic information in device handbook and more in the RAM MegaFunction user guide. 

 DRAM operation depends on the RAM chips and the respective Altera RAM Controller MegaFunction as well. You should probably start with the MegaFunction user guide, read DRAM manufacturer literature as a supplement.