Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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question about signaltap ii

Altera_Forum
Honored Contributor II
‎11-30-2010 03:57 PM
900 Views

hi,all: 

 

...... 

input [2:0]tcm1_stat; 

input clk; 

output alm: 

wire alm; 

 

assign alm=(tcm1_stat==3'b101)?1:0 

...... 

 

why i capture the alm=1 with the signaltap II,but i can't capture the tcm1_stat=3'b101,i am confused. 

 

ps:clk is a global clock,168.04MHz.
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