I've been working on this problem for 3 days but still can't find a solution.
- FPGA cyclone IV EP4CGX75DF27
- FLASH EPCS64
- Quartus prime 16.0
- use the epcs flash controller in the Qsys
- Cable USB-BLASTER to program
- Custom board
How the problem occured :
- I've been working on this board for a long time, and the Flash worked fine.
- last week, I did a little modification to a PIO in qsys(normally this will do nothing to flash), then I program the new .sof into FPGA. and then I can't program the flash any more.
- I tried programming the .sof in Jtag mode, all good.
- I tried programming the .jic in Jtag mode, it says "Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID."
- I tried programming the .pof in AS mode, it says "Current programming device does not support active serial programming mode".
- I re-tried the above tests with old firmware and still can't have my flash back.
So far what i'm sure about:
- USB-Blaster is all good
- FPGA is not damaged
- pin plan, pullup, pulldown are good.
What makes me confused:
- it looks like that my modification has caused the problem but why I can't access to flash anymore?
Hope my question is clear enough.
Tell me if you need more information
Can you check if the MSEL pins are correctly/properly set to AS mode? Also check the power supply to the EPCS64 to ensure the EPCS64 is power up. Use multi-meter or oscilloscope to check the voltage level on the MSEL pins and the EPCS64 power supply pin.
Thanks for your answer.
I should add one more context : the epcs flash used is Cypress Spansion FL064PIF with SPI interface.
I did a few more investigation into the problem, here is what I got:
- I continued testing the first "bug" board
1.1 I tried msel(3 downto 0) = "1011" and "1101" and "1001" and "1010", nothing changed, still can't program the .jic, but .sof could be programmed.
1.2 I tried mesuring VCC, SCLK , CSn, SI and SO of the EPCS chip, it seems at board powering up, the fpga tried to send command to the Flash via SPI, I haven't yet investigated into the detail of those commands.
2. I changed to another "good" board. and I find the reason of BUG.
2.1 I re-programmed several times the new "good" board with old "good" .sof and .jic, all good.
2.2 I then found that I forgot to add the .sdc file in my "bug" project. So I add it and re-compile the project, re-programmed with the .sof and .jic, all good.
2.3 I then re-programmed this board with the "BUG" .jic, and like the first board, this board can't access to the Flash any more, but this time I can re-program the Flash, but when I power down and up the board, the fpga can't be configured by the Flash..
Due to my stupid tests, I now have two valuable boards non functionnal...
I wonder if my .jic wothout .sdc has destroyed the FPGA? but I can still program the .sof to fpga... i think i'm running into a situation super complicated...
Hope you can give me some advices.
Thanks very much.
I assume that you are aware that currently we don't support Cypress Spansion for FPGA AS configuration scheme. JFYI, our Quartus programmer is validated and guarantee to correctly program only EPCQ-A and MT25Q devices. The current direction for low density EPCS and EPCQ EOL is to switch EPCQA device. You can refer to the PDN1708 and AN822 for the details in the following link:
For high density EPCQ/EPCQL(=>256Mb), the plan is moving to support 3rd party flash devices starting from Quartus v18.1. However we have identify MT25Q flash family devices from Micron can be use as replacement for EPCQ/EPCQL(=>256Mb). You can refer to the following link for details:
Anyway, going back to this issue, have you try to perform full erase on the SPI flash device? Try to instantiate the SFL IP into the Cyclone IV design? You can refer to chapter 1.4.1 Instantiating the Intel FPGA Serial Flash Loader IP Core from the AN370 in the following link:
Create a custom design with just the SFL IP instantiated in the Cyclone IV proejct design. Set the unused pin option to reserve as input tristate. Please refer to the attached screen shot. Then recompile the design to get a new sof file.
- Program the new .sof file into the Cyclone IV device.
- Once the .sof file is programmed, perform auto-detect.
- You should be able to see the EPCS/EPCQ device being detect attach to the FPGA if the SFL IP is correctly configured into the FPGA.
- If the EPCS/EPCQ device can be detect in the programmer, then check the Erase option and start to perform full erase.
- After perform full erase successfully, then try to program with the good .jic file.