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21615 Discussions

read/write CFI compatible flash

Altera_Forum
Honored Contributor II
‎09-24-2009 05:06 PM
1,348 Views

I am in the process of extending the capability of a custom FPGA board that contains a Cyclone III and a StrataFlash 256 MByte flash. Currently the board only uses the flash to store configuration data. The FPGA flash interface is configured in AP mode and the flash is currently loaded by an instantiation of the Programmable Flash Loader in HDL. I would like to use this flash as a storage medium for configuration data and user data that would be accessed during operation. Is this a problem somebody has tackled?  

 

As a first step I would like to be able to load the flash with the configuration and user data. Then I would like to configure the device and be able to read random addresses from the memory space representing user data. If that works then I would need to put appropriate user data in and interface that to my custom processing modules. 

  1. Should I use the NIOS II processor to interface to flash? 

  2. If so how would I get the data from the NIOS II processor into custom processing modules on the FPGA. 

  3. How would I inform the NIOS II processor that the custom processing modules are ready for a new piece of data from flash? 

  4. How generalized is the tie in for custom modules in the SOPC Builder? 

  5. Would it be a better approach to write a CFI controller because of ties to custom processing modules? 

  6. Is there a core for a CFI controller that I have overlooked?
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Altera_Forum
Honored Contributor II
‎09-25-2009 06:22 AM
638 Views

Using a CPU is the easiest way of doing it IMHO. There is a CFI flash controller for Nios. 

 

If the data transfer doesn't need to be fast, you can write a simple protocol in software and use PIOs to interface with your modules. As an example a single bit input to the CPU to signal that the module is ready, a parallel output from the CPU with the data, and an additional output to say the data is valid. 

If you need faster transfers, you should have a look at Avalon Streams. You can add a SGDMA to your CPU that can read a block of memory and put it into the stream. The transfer flow can be controlled by your hardware through the ready signal. 

 

Hope this helps!
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Altera_Forum
Honored Contributor II
‎09-28-2009 02:58 PM
638 Views

Thanks, I appreciate the input on the Nios Processors capabilites. I have not worked with an embedded soft processor so the guidance is very helpful. I'm sure I'll have more to add to this thread as I get further into the design.

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