ref. design of S10 with a PCIe enabled 256-bit bursting slave interface (HPTXS) Port

[Altera_Forum]

Hello all, 

 please suggest me a reference design on stratix 10 board with a PCIe , enabled high performance burst interface (HPTXS) port of 256 bit width.  I searched on the net to have a clear understanding about this port, but not found anything. yes, there are 2 paras of information available on the user-guide that available from the tool, but didn't understood anything.  someone please send me a link to understand the functionality of that port, referral design.   some questions  1. can i enable this HPTXS port irrespective of "enable DMA" option that is used to do dma transfers from host to fpga ? 2. once i enable this HPTXS port , i have to select - no. of pages and size of each page (on what basis should i select these two parameters) ?  Regards, Anil

[Altera_Forum]

Hi Anil, 

   --- Quote Start ---  1. can i enable this HPTXS port irrespective of "enable DMA" option that is used to do dma transfers from host to fpga ?  --- Quote End ---   Yes, Refer User guide.   --- Quote Start ---  2. once i enable this HPTXS port , i have to select - no. of pages and size of each page (on what basis should i select these two parameters) ?  --- Quote End ---   Refer Session 7.2.1.2 https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_s10_pcie_avmm.pdf (address + 32 * burst count) <= (page base address + page size )  Let me know if this has helped resolve the issue you are facing or if you need any further assistance.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)