rerun EDA netlist writer

[Altera_Forum]

hi everyone, 

 i just installed altera ver 8.1. started a new project. did RTL simulation. created SDC. but when i click on run gate level timing simulation on the tools menu, i keep getting an info "rerun EDA netlist writer". is quartus not installed correctly? or i'm commiting some ameteurish mistake ?   regards, sumanth

[Altera_Forum]

perhaps a silly question, but did you do a full compilation and see that EDA Netlist Writer ran?

[Altera_Forum]

yes... it completed and the netlist writer didn't even produce warnings......

[Altera_Forum]

Hello, did anyone find a solution to this?

[SFlow]

I'm running on 17.1 and had the same error occur. I was able to resolve the issue by simply restarting compilation. Hope that can help someone​