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rerun EDA netlist writer

Altera_Forum
Honored Contributor II
‎02-02-2009 11:19 AM
3,202 Views

hi everyone, 

 

i just installed altera ver 8.1. started a new project. did RTL simulation. created SDC. but when i click on run gate level timing simulation on the tools menu, i keep getting an info "rerun EDA netlist writer". is quartus not installed correctly? or i'm commiting some ameteurish mistake ? 

 

regards, 

sumanth
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Altera_Forum
Honored Contributor II
‎02-03-2009 09:03 PM
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perhaps a silly question, but did you do a full compilation and see that EDA Netlist Writer ran?

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Altera_Forum
Honored Contributor II
‎02-04-2009 02:51 AM
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yes... it completed and the netlist writer didn't even produce warnings......

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Altera_Forum
Honored Contributor II
‎07-15-2013 03:26 PM
2,262 Views

Hello, did anyone find a solution to this?

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SFlow
Beginner
‎09-21-2018 06:38 PM
2,262 Views

I'm running on 17.1 and had the same error occur. I was able to resolve the issue by simply restarting compilation. Hope that can help someone​

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