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sRama28
Beginner
257 Views

signal type not available in QSYS

hi 

i have porting one board from CYCLONE to MAX 10.

in my design contain ADC interface then the data will transfer  to NIOS through DMA.

so we have created some control signal to do handshake between FPGA and NIOS.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec_1_3....

 

referred this document which has one signal dataavilable. whenever my FIFO having data which will trigger the signal to NIOS then the NIOS will read it.

but now i m using QUARTS 15.0 where data available signal is not available in avalon memory map interface .

 

so what is the replacement signal for that.

PROCESS FLOW:

1.dataavilable will go to NIOS from FPGA [need alternate signal for this]

Avalon interface document [2010 edition]-3.5.4.4 section flow control .

 2.read signal will reach FPGA from NIOS.[this is available]

Reply me INTEL please

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6 Replies
sstrell
Honored Contributor II
233 Views

That signal has been deprecated from the Avalon memory-mapped standard.  I don't know what FIFO IP you are using or if you are building your own, but usually there would be a "not empty" signal or a status register to read to see if data is available.

If you use Avalon streaming instead of memory-mapped, you can make use of the valid and ready signals that are part of that standard for data streaming in and out of the FIFO.

BoonBengT_Intel
Moderator
226 Views

Hi @sRama28,

Hope this message find you well, please do let if the issues still persist, and we would be more than happy to look into it or any other clarification that we can help you with.

Warm regards. 

sRama28
Beginner
217 Views

hi Intel

1.not empty signal is not available in avalon memory mapped slave interface.

2.status register method - means using PIO register and writing the value to 1 after FPGA FIFO got data.please confirm these point.

we need below signals in avalon memory mapped slave interface 

1.chip select

2.read enable

3.read data 

4.data available /not empty/status register concept[please explain]

BoonBengT_Intel
Moderator
172 Views

Hi @sRama28,

Apologies for the long wait and thank you for your patients.
Back to the initial question you have on the replacement for dataavailable signals, alternatively we woudl recommend to use the Avalon streaming as mention.
Attached is the user guide on how to implement the ADC on Max 10 devices.
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_adc.pdf

Warm regards.

BoonBengT_Intel
Moderator
169 Views

Hi @sRama28,

Just to add on, for the second part of the question, the 'not ready signals' is readily available in the Avalon-st
As for the second part of the question, more details of the signals as explained below:
- chip select (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf#...)
- read enable ((https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf#...))
- read data (signal available in avalon-mm and are required)
- data available (as mention has been deprecated, recommends using avalon-st)

Warm regards.

BoonBengT_Intel
Moderator
129 Views

Hi @sRama28,

Hope this message find you well and good day, as we do not receive any response from you to the previous clarification that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 

 

Warm Regards

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