Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

simulation

Altera_Forum
Honored Contributor II
‎04-16-2010 03:43 PM
1,084 Views

hello  

 

i want to simulate frequency devidor with devision of 50 000 000 (from 50 MH z to reach 1 second period ) but how can i simulate this ... if i try with modelsim it takes many time to calculate the result .... is there faster way ?
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎04-16-2010 09:46 PM
385 Views

For functional simulation you only need to try any small test counter. Then the 1 sec issue can be thought of as just a scaled case. 

 

For timing verification, use hardware e.g. led flashing rate.
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.