stmmac_dvr_probe: warning: cannot get CSR clock

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I'm trying to boot from QSPI cyclone V soc devkit, i prepared and flash the QSPI with the files preloader, socfpga.dtb, u-boot.img, uImage (cannot read zImage), socfpga.rootfs.jffs2 

in ubuntu host machine the boot process hand up with "stmmac_dvr_probe: warning: cannot get CSR clock" massage   U-Boot SPL 2012.10 (Nov 21 2013 - 13:36:56) SDRAM: Initializing MMR registers yehuda SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED SF: Detected N25Q00 with page size 65536, total: 134217728     U-Boot 2012.10 (Nov 28 2013 - 10:34:59)   CPU : Altera SOCFPGA Platform BOARD : Altera SOCFPGA Cyclone 5 Board DRAM: 1 GiB MMC: DESIGNWARE SD/MMC: 0 SF: Detected N25Q00 with page size 65536, total: 134217728 *** Warning - bad CRC, using default environment   In: serial Out: serial Err: serial Net: mii0 Warning: failed to set MAC address   Hit any key to stop autoboot: 0 SF: Detected N25Q00 with page size 65536, total: 134217728# # Booting kernel from Legacy Image at 00007fc0 ...  Image Name: Linux-3.12.0-rc3-00186-gc31eeac  Image Type: ARM Linux Kernel Image (uncompressed)  Data Size: 2182032 Bytes = 2.1 MiB  Load Address: 00008000  Entry Point: 00008000# # Flattened Device Tree blob at 00000100  Booting using the fdt blob at 0x00000100  XIP Kernel Image ... OK OK  Loading Device Tree to 0fffa000, end 0fffef8a ... OK   Starting kernel ...   Booting Linux on physical CPU 0x0 Initializing cgroup subsys cpuset Linux version 3.12.0-rc3-00186-gc31eeac (yehuda@DT-Cyclone5) (gcc version 4.7.3 20121106 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2012.11-20121123 - Linaro GCC 2012.11) )# 1 SMP Thu Nov 28 08:20:04 IST 2013 CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache Machine: Altera SOCFPGA, model: Altera SOCFPGA Cyclone V Truncating RAM at 00000000-3fffffff to -2f7fffff (vmalloc region overlap). Memory policy: ECC disabled, Data cache writealloc BUG: mapping for 0xfffec000 at 0xfffec000 out of vmalloc space PERCPU: Embedded 8 pages/cpu @c0a45000 s11328 r8192 d13248 u32768 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 193040 Kernel command line: console=ttyS0,57600 root=/dev/mtdblock1 rw rootfstype=jffs2 PID hash table entries: 4096 (order: 2, 16384 bytes) Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) Memory: 766844K/778240K available (2931K kernel code, 150K rwdata, 880K rodata, 187K init, 215K bss, 11396K reserved) Virtual kernel memory layout:  vector : 0xffff0000 - 0xffff1000 ( 4 k  fixmap : 0xfff00000 - 0xfffe0000 ( 896 k  vmalloc : 0xf0000000 - 0xff000000 ( 240 M  lowmem : 0xc0000000 - 0xef800000 ( 760 M  modules : 0xbf000000 - 0xc0000000 ( 16 M  .text : 0xc0008000 - 0xc03c0e34 (3812 k  .init : 0xc03c1000 - 0xc03efc40 ( 188 k  .data : 0xc03f0000 - 0xc0415ab8 ( 151 k  .bss : 0xc0415ab8 - 0xc044b800 ( 216 k SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 Hierarchical RCU implementation. NR_IRQS:16 nr_irqs:16 16 sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949ms Console: colour dummy device 80x30 Calibrating delay loop... 1594.16 BogoMIPS (lpj=7970816) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 512 CPU: Testing write buffer coherency: ok CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 Setting up static identity map for 0xc02c8e48 - 0xc02c8ea0 CPU1: Booted secondary processor CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 Brought up 2 CPUs SMP: Total of 2 processors activated. CPU: All CPU(s) started in SVC mode. devtmpfs: initialized VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 NET: Registered protocol family 16 DMA: preallocated 256 KiB pool for atomic coherent allocations L310 cache controller enabled l2x0: 8 ways, CACHE_ID 0x410030c9, AUX_CTRL 0x02060000, Cache size: 512 kB of_amba_device_create(): amba_device_add() failed (-2) for /soc/amba/pdma@ffe01000 hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers. hw-breakpoint: maximum watchpoint size is 4 bytes. bio: create slab <bio-0> at 0 SCSI subsystem initialized pps_core: LinuxPPS API ver. 1 registered pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> PTP clock support registered Switched to clocksource timer3 NET: Registered protocol family 2 TCP established hash table entries: 8192 (order: 4, 65536 bytes) TCP bind hash table entries: 8192 (order: 4, 65536 bytes) TCP: Hash tables configured (established 8192 bind 8192) TCP: reno registered UDP hash table entries: 512 (order: 2, 16384 bytes) UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) NET: Registered protocol family 1 NTFS driver 2.1.30 [Flags: R/W]. msgmni has been set to 1497 io scheduler noop registered (default) Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 194, base_baud = 6250000) is a 16550A console [ttyS0] enabled brd: module loaded stmmac - user ID: 0x10, Synopsys ID: 0x37  Ring mode enabled  DMA HW capability register supported  Enhanced/Alternate descriptors  Enabled extended descriptors  RX Checksum Offload Engine supported (type 2)  TX Checksum insertion supported  Enable RX Mitigation via HW Watchdog Timer stmmac_dvr_probe: warning: cannot get CSR clock  can someone please advise what do i do wrong? Thanks