Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

stratix10 configuration

allen18
New Contributor II
1,680 Views

hello,

     I am using quartus Pro 22.3 , device ( stratix10 1SX110HN2F43I2VG ) , flash( MT25QU512).

     When I load the flash using JTAG with a JIC file, and then power cycle the board, FPGA can be successfully configured.

      Now, we plan to use a Single-Chip Microcomputer to load the flash via the AS Configuration method. This microcontroller need a binary file. In the past, when using Xilinx chips, along with generating a bit file, a corresponding bin file would also be generated. Loading this bin file into the flash and then powering up would configure the FPGA. How can I obtain a similar binary file from quartus Pro? I have tried generating RPD and RBF files, experimenting with both big-endian and little-endian formats, but directly writing these files to the flash does not successfully configure the FPGA. How can I obtain a bin file similar to Xilinx's, which can be directly written to the flash for FPGA configuration?

     

Labels (1)
0 Kudos
1 Solution
allen18
New Contributor II
1,562 Views

allen18_0-1722246989901.png

I used the RPD file generated simultaneously with the JIC file generation, and also enabled bit swap. This configuration was successful.

View solution in original post

0 Kudos
3 Replies
allen18
New Contributor II
1,646 Views

After programming jic file by Jtag, I read 8 bytes of data from the flash. Then, I searched for these data in the .rpd file and found them indeed present, but not starting from address 0. Can I extract all these data from  RPD file in some way, create a BIN file, and load it into flash using microcontroller, ensuring successful configuration of the FPGA as well?

0 Kudos
allen18
New Contributor II
1,563 Views

allen18_0-1722246989901.png

I used the RPD file generated simultaneously with the JIC file generation, and also enabled bit swap. This configuration was successful.

0 Kudos
Fakhrul
Employee
1,537 Views

Hi allen18,


Sorry I missed you post. I am glad to hear that the issue is resolved, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Regards,

Fakhrul


0 Kudos
Reply