unable to create symbol file for current file (Verilog HDL file) in Quartus IIweb13.1

[Altera_Forum]

Hi, 

I am unable to create symbol file for current file (Verilog HDL file) in Quartus II web edition 13.1. Compilation report shows 'Data not available'. plz help me !

[Altera_Forum]

why not post the verilog file here...

[Altera_Forum]

Hi Tricky, 

I am trying to run 'My_first_fpga' tutorial on my cyclone III starter board, verilog code is as below:  // This is an example of a simple 32 bit up-counter called simple_counter.v // It has a single clock input and a 32-bit output port module simple_counter (input clock , output reg [31:0] counter_out); always @ (posedge clock)// on positive clock edge begin counter_out <=# 1 counter_out + 1;// increment counter end endmodule// end of module counter

[Altera_Forum]

have you created a project?

[Altera_Forum]

Hi, 

 I am also doing that tutorial and I have the same problem. I created a project (just as instructed). Chitranshvarun, were you able to resolve this issue? Perhaps I should add that I am using this EP4CE6E22C8N FPGA rather than one of the recommended FPGAs...  Thanks in advance, Chandran