Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

using MAX 10M50 ADC+DAC

Altera_Forum
Honored Contributor II
‎02-27-2018 04:50 PM
1,245 Views

Hey, 

i want to get the input data from ANAIN1 SMA, through ADC and then to the DAC8551, and then to get it out through DACOUT SMA. 

 

is there any reference design using DAC and ADC together? 

how do i sync the clock and the data? 

how do i implement the DAC8551 in VHDL? 

:confused::confused::confused: 

 

thanks Dor
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.