vhdl-car park monitoring system

[Altera_Forum]

hi guys, i am new with vhdl and i have to write the following programm, the thing is tha i find it really hard and i would like some help. 

 1. The car park counts the number of cars parked inside. The maximum count is 1024 2. The car park signals an error condition if a car leaves when the count is 0 or a car enters when the count is 1024. 3. The car park reports the time when a car has entered or leave in hours and minutes. 4. The sensors which inform the car park system that a car is present enable their outputs as long as a car is situated in front of them. This means that the amount of time the sensor is on is variable (cars moving at different speeds in front of the sensors). 5. One car entering and one car leaving at the same time is perfectly valid. 6. An external MIDNIGHT SYNC signal informs the system when it is midnight (useful to synchronize the time reporting circuit). 7. Two general RESET/CLEAR inputs are available. 8. Two outputs FULL/EMPTY indicate when the car is full or empty 9. An output CAR COUNT indicates how many cars are inside the car park. 10. A CLOCK input with a clock period of 1 ms is available.    thank uuuu :):)

[Altera_Forum]

What are your specific problems? we wont do your work for you.

[Altera_Forum]

i ve done this so far: 

 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is generic (n:natural:=1024); port ( c, clk:in std_logic; reset;in std_logic;  cout: out std_logic_vector( 1023 downto 0); end counter architecture behv of counter is begin  process (clk, reset, cout) begin if (reset='1') then cout<=(others=>'0'); elsif ( rising_edge(clk)) then if (up_down='1') then count <=count+1 else count<=count-1 end if; end if; end process; cout<=count; end architecture;    synchronous reset with clock enable;  process (clk) begin if rising_edge(clk) then if enable='1' then Q<=D; end if; end if; if reset='1' then  Q<='0'; end if; end process;

[Altera_Forum]

Your starting point will be to design a counter 0~1023 on your clk. 

at reset it is 0 then goes up or down per car entry/exit. If it is zero then and a car left then output alarm ...etc.   good luck

[Altera_Forum]

i also thought of adding a digital clock in the program in order to show the hour, minutes and seconds when the car enters or leaves 

  entity digi_clk is port (clk1 : in std_logic;  seconds : out std_logic_vector(5 downto 0);  minutes : out std_logic_vector(5 downto 0);  hours : out std_logic_vector(4 downto 0)  ); end digi_clk;  architecture Behavioral of digi_clk is signal sec,min,hour : integer range 0 to 60 :=0; signal count : integer :=1; signal clk : std_logic :='0'; begin seconds <= conv_std_logic_vector(sec,6); minutes <= conv_std_logic_vector(min,6); hours <= conv_std_logic_vector(hour,5);   process(clk1)  begin if(clk1'event and clk1='1') then count <=count+1; if(count = 50000000) then clk <= not clk; count <=1; end if; end if; end process;  process(clk)  begin if(clk'event and clk='1') then sec <= sec+ 1; if(sec = 59) then min <= min + 1; end if; if(min = 60) then hour <= hour + 1; min <= 1; end if; if(hour = 24) then hour <= 0; end if; if(sec = 60) then sec <= 1; end if; end if; end process;  end Behavioral;

[Altera_Forum]

To add more: 

 First you need to define your VHDL module Inputs/outputs. I suggest these as possible candidates, plus others as needed:   inputs: reset (std_logic) clk (std_logic) car_in(std_logic) car_out(std_logic) midnight_sync(std_logic)     outputs: error(std_logic) full(std_logic) empty(std_logic) number_of_cars_in(std_logic_vector(1023 downto 0)   With regard to time of entry etc. You will need to have a separate module to generate time clock.

[Altera_Forum]

You are on track but your time clock does not look right to me. 

 first "count" must be constrained integer. your clk input is 1 msec period hence 1000 periods means 1 second let count run between 0 ~ 999   do not produce gated clk (clk = not clk).   run all counting on system clk  process(reset,midnight_sync,clk) if reset or midnight_sync .... elsif(rising_edge(clk))then if msec_count /= 999 then msec_count <= msec_count + 1; else msec_count <= 0; if sec_count /= 59 then sec_count <= sec_count + 1; else sec_count <= 0; if min_count /= 59 then min_count <= min_count + 1; else min_count <= 0; if hr_count /= 23 then hr_count <= hr_count + 1; else hr_count <= 0; end if; end if; end if; enf if; end if;