vhdl querry

[Altera_Forum]

Hello Friends, 

 I am new to VHDL and I have a couple of querries. Kindly help me out if possible -   1) If-else loop in VHDL. Now, what I understand is that VHDL code is synthesised into hardware (gates/mux..etc) using a synthesizer. How is an if-else loop created in hardware? The -f-else is a sequential statement. Will it run/be executed at the same clock cycle or the next ? For eg - in the code shown  write_req <= '1'; write_req:process(phy_clk)  begin  if rising_edge(phy_clk) then  if reset_phy_clk = '1' then  write_req_1 <= '0';  write_req_2 <= '0';  else  write_req_1 <= write_req;  write_req_2 <= write_req_1;  end if;  end if;  end process p_data_req;  After how many cycles is write_req_2 asserted ? Can anyone kindly explain this pls? Also, can if-else statements be used to generate/synthesize combinational circuits or only sequential ? Can anyone point me to a doc which shall explain in details how vhdl code is executed(order of execution/timing) and also how it is mapped into hardware ?  2) What is a latch ?  fifo_o_addr_temp <= fifo_o_addr when fifo_o_addr_temp /= fifo_o_addr else fifo_o_addr_temp;  Will doing the above action create a latch ? How so? Is creating a latch in code a good practise or bad?  Regards, Vinod Karuvat.

[Altera_Forum]

Look at sensitivity-list topic in VHDL textbook. 

 DFF is edge sensitive. LATCH is level sensitive.

[Altera_Forum]

To design 3-bit parity generator/checker that has three data inputs (A to C) and one odd parity output (odd_out). When the number of high level input is odd, odd_out is kept HIGH. Likewise, if the number of high level input is even, odd_out is LOW. The design of this generator is to be written in VHDL. Produce the truth table for this generator and treat C as the MSB.

[Altera_Forum]

--- Quote Start ---  To design 3-bit parity generator/checker that has three data inputs (A to C) and one odd parity output (odd_out). When the number of high level input is odd, odd_out is kept HIGH. Likewise, if the number of high level input is even, odd_out is LOW. The design of this generator is to be written in VHDL. Produce the truth table for this generator and treat C as the MSB.  --- Quote End ---    cool thanks

[Altera_Forum]

???? 

 What is this message ??

[Altera_Forum]

library ieee; 

use ieee.std_logic_1164.all;  entity 3-bit parity generator/checker is  port  (  c : in std_logic;  b : in std_logic;  a : in std_logic;  odd_out : out std_logic;     );  end 3-bit parity generator/checker;    architecture arc of 3-bit parity generator/checker is    signal result : std_logic;    begin  process (a, b, c)  begin  result <= a xor b xor c;  odd_out <= result;     end process;    end arc;   I compile this VHDL but got errors and don't know what wrong with this 

[Altera_Forum]

--- Quote Start ---  I compile this VHDL but got errors and don't know what wrong with this  --- Quote End ---   It's a simple syntax error in the port definition. Read the first error message thoroughly and try to understand it.    --- Quote Start ---  2) What is a latch ?  fifo_o_addr_temp <= fifo_o_addr when fifo_o_addr_temp /= fifo_o_addr else fifo_o_addr_temp;  Will doing the above action create a latch ? How so? Is creating a latch in code a good practise or bad?  --- Quote End ---   It will create nothing except a "wire" assignment fifo_o_addr_temp <= fifo_o_addr, because the code is useless. With a more meaningful condition, it will create a latch. Latches should be avoided in FPGA synthesis, but can't in special cases.

[Altera_Forum]

--- Quote Start ---  Hello Friends,  I am new to VHDL and I have a couple of querries. Kindly help me out if possible -   1) If-else loop in VHDL. Now, what I understand is that VHDL code is synthesised into hardware (gates/mux..etc) using a synthesizer. How is an if-else loop created in hardware? The -f-else is a sequential statement. Will it run/be executed at the same clock cycle or the next ? For eg - in the code shown  After how many cycles is write_req_2 asserted ? Can anyone kindly explain this pls? Also, can if-else statements be used to generate/synthesize combinational circuits or only sequential ? Can anyone point me to a doc which shall explain in details how vhdl code is executed(order of execution/timing) and also how it is mapped into hardware ?   --- Quote End ---    VHDL code is synthesised into gates and registers. So if/elsif/else trees get converted to logic, and if it's inside a clocked process then this logic is registered. All signal assignments take place on every clock cycle. So in this case, write_req_2 is asserted 2 clock cycle after write_req_1. VHDL code is never executed.    --- Quote Start ---   2) What is a latch ?  fifo_o_addr_temp <= fifo_o_addr when fifo_o_addr_temp /= fifo_o_addr else fifo_o_addr_temp;   --- Quote End ---    A latch is a memory device. registers are latches. Latches are created when data is stored and all events on a signal are not covered.

[Altera_Forum]

Dear Friends, 

 Thank you for ur response. I am grateful.    --- Quote Start ---  VHDL code is synthesised into gates and registers. So if/elsif/else trees get converted to logic, and if it's inside a clocked process then this logic is registered. All signal assignments take place on every clock cycle. So in this case, write_req_2 is asserted 2 clock cycle after write_req_1. VHDL code is never executed.  --- Quote End ---    You mentioned if/else/elsif gets converted to logic. What exactly do u mean by that sir? Is it converted to registers and gates?   What I understand is this - inside a process if there is merely an if-else loop it is a combinational design. But, when the if-else is inside a clock (i.e - if rising_edge(clock)..etc) then it is converted into a sequential circuit.  Also why do you say that VHDL code is never executed ?  How does one decide when to use combainational or sequential circuits ? Pls advice me sir.    --- Quote Start ---  A latch is a memory device. registers are latches. Latches are created when data is stored and all events on a signal are not covered.  --- Quote End ---      Why is it said that using lateches in VHDL is a bad practise ?  Thank you very much indeed.  Regards, Vinod Karuvat.

[Altera_Forum]

--- Quote Start ---    You mentioned if/else/elsif gets converted to logic. What exactly do u mean by that sir? Is it converted to registers and gates?    --- Quote End ---   yes    --- Quote Start ---    What I understand is this - inside a process if there is merely an if-else loop it is a combinational design. But, when the if-else is inside a clock (i.e - if rising_edge(clock)..etc) then it is converted into a sequential circuit.   --- Quote End ---    Yes    --- Quote Start ---   Also why do you say that VHDL code is never executed ?  How does one decide when to use combainational or sequential circuits ? Pls advice me sir.   --- Quote End ---    VHDL is not executed like software. Software is converted to machine code that is executed in order. VHDL is converted to logic that all runs in parrallel.   All logic circuits are usually combinations of cominatorial and sequential logic. FPGAs can do either.       --- Quote Start ---   Why is it said that using lateches in VHDL is a bad practise ?   --- Quote End ---    because you cant guarantee the timing. So all sorts of bad things can happen.

[Altera_Forum]

Dear Friend , 

 Thank you very much indeed for all the responses.  I am just rephrasing my understanding of the clocked sequential circuit used in an earlier post.  write_req <= '1'; write_req:process(phy_clk)  begin  if rising_edge(phy_clk) then  if reset_phy_clk = '1' then  write_req_1 <= '0';  write_req_2 <= '0';  else  write_req_1 <= write_req;  write_req_2 <= write_req_1;  end if;  end if;  end process p_data_req;  In the above case. at time  t0 - it will check rising edge of clock,reset_phy_clk and if both are satisfied  t1 - in next cycle write_req_1 <= '0' write_req_2 <= '0'. and it goes into the else part. t2 - write_req_1 <= write_req and write_req_2 <= write_req_1 is done here.  Kindly comment if my understanding is correct. So basically it is a synchronous sequential circuit.  Reagards, Vinod Karuvat.

[Altera_Forum]

not exactly... at each clock rising edge, if reset_phy_clk is 1 then your write req will be 0, and if it isn't you will shift the values between the write_req. This code is a shift register with a synchronous reset. 

Compared to your description, t0 and t1 are the same clock cycle, and t2 is a clock cycle after.