vhdl syntax error

[Altera_Forum]

hello, 

 here is part of my vhdl codes.  ce : in std_logic; addr : in std_logic_vector (15 downto 0);  process(ce, addr)  variable gpio_enable : std_logic ; begin   case ce and addr(7 downto 5) is --line 58  when "001" => gpio_enable <= '1';  when others => gpio_enable <='0';  end case; end process;  when i compile th design, i got an error :  Error (10327): VHDL error at wb_io.vhd(58): can't determine definition of operator ""and"" -- found 0 possible definitions  Can anyone help me ??

[Altera_Forum]

Hi, 

 I believe you want to concatenate rather than "and". Try this  signal sub_addr : std_logic_vector(3 downto 0);  -- sub_addr <= ce & addr(7 downto 5);  case sub_addr is when "1001" =>   you might as well just use a single combinatorial assignment  Kaz

[Altera_Forum]

ce : in std_logic; 

addr : in std_logic_vector (15 downto 0);  -----------------------------------------------------  gpio_enable <= '1' when (ce='1' and addr(7 downto 5)="001" ) else '0';   -----------------------------------------