Presently I am implementing an ASIC IP in FPGA. Some of the ASIC source files are .vs and .vm file extensions.
What are .vs and .vm file extensions? Are they supported in quartus for compilation.
Even though I compile the project in quartus. the hierarchy window shows the Project in a different way than usual quartus project. The snapshot of the hierarchy view is attached. What could be the reasons for this.
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