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Beginner
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we have below two questions 1.Can we use fpll in arria10 devices for user logic clock generation. we chose fpll as the normal pll is not supported fractional divider value 2. Mentioned second question below

2. while generating two frequencies(360,156.25) from one pll we are not able to get exact frequency in one of the frequency. do v need to use seperate plls for generating these two frequencies.

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Answer #1 : yes , Arria 10 FPLL can be used in Fabric side.

Answer #2 : Can you check that you are getting any warnings after compliation ; My past experience I see valuses such as 306.7 FPLL vco not able to converge where 306.5 was working fine.

 

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Beginner
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​1. we are using fPLL in Core Mode. But we are getting below error as we have provided input from FPGA pin.

Error(11215): Input port "REFCLK" of "CMU_FPLL_REFCLK_SELECT" cannot connect to PLD port "O" of "IO_INPUT_BUFFER" for atom "fpga_clk~input".

 To avoid above error, Do we need to provide internal clock signal to input of fPLL instead of PAD clock.

We have created one simple counter logic, to make sure fPLL works for user logic.

Clock path is as below.

FPGA pin to fPLL input

Output clock from fPLL is used for running a 4 bit counter. Counter bits are given to on board LEDs.

 

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