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where can find the user guide of "Avalon-MM Clock Crossing Bridge IP" in Quartus 19.2 ?

JET60200
New Contributor I
224 Views

Hello,

 

I check customer PCIE AVMM DMA design , and find an "Avalon-MM Clock Crossing Bridge" module inside. BUt from PLatform Designer, I don't find the IP 's user guide ?

 

Where can I find ?

 

Thanks

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1 Solution
RichardTanSY_Intel
199 Views

Bridges are used to control the topology of a Qsys system. The Avalon-MM Clock Crossing Bridge transfers Avalon-MM commands and responses between different clock domains. You can also use the Avalon-MM Clock Crossing Bridge to bridge between AXI masters and slaves of different clock domains. You can refer to the link below for more information.

Reference: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-platform-designer...

 

p.s. Don’t forget to Reply, and Select the Best Answer. :)

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4 Replies
RichardTanSY_Intel
200 Views

Bridges are used to control the topology of a Qsys system. The Avalon-MM Clock Crossing Bridge transfers Avalon-MM commands and responses between different clock domains. You can also use the Avalon-MM Clock Crossing Bridge to bridge between AXI masters and slaves of different clock domains. You can refer to the link below for more information.

Reference: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-platform-designer...

 

p.s. Don’t forget to Reply, and Select the Best Answer. :)

View solution in original post

JET60200
New Contributor I
199 Views

That's very useful guidance , Thanks for your reply @ShyanYewT_Intel​  :)

JET60200
New Contributor I
199 Views

Hi @ShyanYewT_Intel​ ,

 

Inside Quartus Standard Edition 18.1, I wanto create a proect example , and instantiate an "Avalon-MM Clock Crossing Bridge IP" in IP Catalog,

But I don't find where can I ADD IP of "avmm clock cross bridge"? Can you give some advice ?

 

avmm_clock_bridge.png

RichardTanSY_Intel
199 Views

You can only find it in the IP catalog of platform designer. Go to Tools > Platform Designer.

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