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What the problem is about the circuit?

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Hello everyone.

I made a circuit like this.註解 2020-06-11 165256.png​The Simulation is like this.

註解 2020-06-11 165349.png

 

The TFF has triggered before the "Toggle" single rise up.

I use Quartus FPGA lite 18.1 and 19.1. The simulation is same.

I tried to program it to fpga dev board(EPM240T100C5N). The situation is also same.

I asked this problem to our school teachers.They also can't solve this problem.

I wanna know why the TFF is triggered to high before Clk and "test" signal at the start time.

So what the circuit problem is? Thank you.

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Retired Employee
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Your input to the flip-flop is low because you're ANDing the high Toggle and the low Q_Bar, so the flip-flop doesn't toggle.

 

https://en.wikipedia.org/wiki/Flip-flop_(electronics)#T_flip-flop

 

#iwork4intel

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Retired Employee
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Your input to the flip-flop is low because you're ANDing the high Toggle and the low Q_Bar, so the flip-flop doesn't toggle.

 

https://en.wikipedia.org/wiki/Flip-flop_(electronics)#T_flip-flop

 

#iwork4intel

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Moderator
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Hi,

 

There is low toggle resulted by AND gate as high input toggle and low q_bar

Change it to OR gate to make it toggle.

 

Thanks,

Regards

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I Know the TFF is triggered to high and then it can't not be toggle again.But the TFF is not trigger by CLK or "test" signal.It toggle automatically at the start time.

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Highlighted
Retired Employee
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I'm not sure I understand what you are saying here. As suggested, if you used an OR gate instead of an AND gate, it would work.

 

#iwork4intel

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