which SRAM that FPGA configuration will be loaded?

[Altera_Forum]

Dear experts, 

 I am a new with Altera device (Cyclone III EP3C25) and wonder if someone can help me answer below question:  During boot-up when the FPGA configuration file (.sof) is loaded to SRAM, which SRAM will be used? Is it on-chip SRAM (M9K)?

[Altera_Forum]

The .sof file can load data to both the user accessible SRAM (M9K) and the internal SRAM that controls the logical elements.

[Altera_Forum]

--- Quote Start ---  Dear experts,  I am a new with Altera device (Cyclone III EP3C25) and wonder if someone can help me answer below question:  During boot-up when the FPGA configuration file (.sof) is loaded to SRAM, which SRAM will be used? Is it on-chip SRAM (M9K)?  --- Quote End ---    FPGAs have a large number of configurable elements: the LUTs/Logic Elements, the I/O elements, the interconnect matrix and other specialized elements such as M9K, multpliers, PLLs, etc, etc.  Each and every element needs to have it's configuration set somehow. In a SRAM based FPGA, as are Cyclone and Stratix (and Spartan and Virtex), the configuration values are held inside the FPGA by small SRAMs. For example, for each 4 input LUT, there's a 16x1 bit SRAM that holds the look-up table.  When the FPGA configuration (the .sof) is loaded, it's loaded into each and every of those SRAMs.

[Altera_Forum]

Daixiwen, rbugalho, 

 Thank you very much for the answers. It became clear to me now:)

[Altera_Forum]

Hello, buy a DE2 development board for a project. and need to read 960 bits from SDRAM to the FPGA in parallel, but I have not found a way to do this, please if anyone can help thank you. 

 Greetings from Colombia

[Altera_Forum]

Add a NiosII and a SDRAM controller (both are SOPC IP cores), then you can read your 960 bits