i am trying to generated a pulse for my converter. In Quartus everything is fine and i have seen the output waveform in digital oscilloscope. I want to see the waveform in Questa-Intel FPGA but it is showing blue line after giving a clock.
I have attacehd a .qar file also along with a image showing blue line.
i have tried to see the waveform in university program VWF also there also waveform is not coming . are this two things related and how to solve it please guide me to solve it.
I am just giving a clock in Questa only, so do I need to design input stimuli also?
as it is comparing constant and counter it is generating a pulse with a required frequency of 20khz. I am getting output from lpm_compare.
I am not much aware of how to design a testbench in Quartus for a block diagram design.
please guide me in designing the same.
To perform Questa simulation, you need to have a test bench. You may refer to this https://community.intel.com/t5/Intel-Quartus-Prime-Software/Creating-test-bench-code-on-Quartus-prime/m-p/586458 on creating a test bench.
Next, for VWF simulation,
- The device family used needs to change to the supported family devices (Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, MAX II, MAX V, Stratix IV), either one will do.
- Compile the design.
- Create a new University Program VWF.
- Set the nodes and run timing simulation.
Then, you should be able to get the output result. By setting the first_project.bdf to top-level entity, from your design, this is the VWF waveform generated I obtained (ss_VWF_waveform).
I am also getting the same waveform.
But while programming and seeing the waveform in oscilloscope i am getting a pulse of 20khz at output of ageb .
The pin_name1 is also at low here in waveform but in oscilloscope it is also coming correctly.
why here the waveform is at low instead of any pulse?
what may be the error due to which this are not coming?
Expected behaviour of output aged will be 50khz pulse(for my case in oscilloscope i got waveform as attached) and for pin_name1 it should generate same clock in ouput which is 50Mhz (In oscilloscope it is coming sinusoidal of 50khz because of filters ) . Both outputs should be a pulse only, of different frequency.
Thanks for attaching the image.
I managed to modify and simulate your design to get the expected output waveform. These are some changes made.
First, I would recommend you to design the project using Verilog HDL or VHDL rather than BDF file as Questa simulation does not support BDF. That's why you can't see the output waveform when the BDF is set as top-level module.
Second, it is better to run the simulation in Questa than in VWF. Because there is a bug when running simulation in VWF, sometimes it does not work. You would require to create a test bench for to run in Questa.
Third, the first_project.v you created was not function as described in the BDF as the LPM used were not functioned correctly.
Here is the test project I created that works similar as your design. It is designed using the Verilog HDL file and attached with a test bench to run simulation in Questa. The design uses LPM IP cores and instantiate them in the top-level module. After compiling, run RTL simulation, you should be able to see the expected output waveform in Questa.
You may check out some useful links here:
Introduction to Intel® FPGA IP Cores - Generating IP Cores
Intel FPGA Integer Arithmetic IP Cores User Guide
Hope this might help you. Thanks.
We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.