- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
(ftp://download.intel.com/design/Pentium4/manuals/25366719.pdf) contains the opcode for a multi-byte NOP instruction. The opcode is
0F 1F mod-000-rm
The multi-byte NOP can have any length up to 9 bytes. Quite useful for alignment.
The manual says that this multi-byte NOP works on all processors with family number 6 or F, which is all Intel processors back to Pentium Pro (except Pentium MMX). I have verified that it works. I was surprised to discover that it works also on an AMD64 processor, although it is not documented in AMD manuals. I didn't find it on any website of undocumented opcodes.
How come that this opcode has been kept secret for so many years? Why is it made official now? How come it works on AMD processors when noone else has discovered it, and AMD recommends the opcode 66 66 66 90 for multibyte NOP?
I guess this is not the right place to ask about AMD processors, but how do I safely detect whether the multi-byte NOP is supported on an AMD processor? There is no use for this opcode unless you have an absolutely safe method of detecting whether it is supported, and this detection method works on all brands.
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
http://www.sandpile.org/post/msgs/20004129.htm
Opcodes 0F 18 through 0F 1F are hinting NOPs reserved for future use. This is the reason why it doesn't cause exceptions on old processors back to Pentium Pro. I tried it on a Pentium MMX and it gives an exception.
Are the hinting NOP codes official? And when were they first made so?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
We are forwarding your question to our engineering contacts. We will let you know how they respond.
Regards,
Lexi S.
IntelSoftware NetworkSupport
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thank you for your patience. The response we received from our engineering contacts is that the informationunder discussionis likelyIntel Confidential, and therefore would require an NDA to be in place prior to disclosure.
If your company has its own Intel representative, you may wish to inquire whether they are able to assist with this inquiry. Your company's Purchasing Department will normally have your Intel representative's contact information. If you have no contact, please see http://www.intel.com/buy/networking/design.htm under "Design Components".
If your location is not listed, please see an Intel Authorized Distributor and ask for a Field Application Engineer (FAE). Our Intel Authorized Distributor list is also linked from the URL above.
Regards,
Lexi S.
IntelSoftware NetworkSupport
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Sorry for bringing up the old thread folks, but I would like some clarification on this. I am not interested in those details Agner was pursuing, but I would really like to know the following:
- Why regular NOPs weren't enough?
- Assuming that those hinting NOP instructions will have variable length (because they are most likely intended for padding), how exactly are they meant to improve decoding speed when current decoding bottleneck for x86 is in determining the instruction boundaries?
So, any chance to at least get the answers to the above questions without the NDA Lexi?
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page