Ivy Bridge performance monitoring events CYCLE_ACTIVITY.*?

[JimH]

Hi,

In "Intel 64 and IA-32 Architectures Optimization Reference Manual" (April 2012) B.3.2.3 Memory Bound Characterization, it says that: "In Intel microarchitecture code name Ivy Bridge, a new performance monitoring event 'CYCLE_ACTIVITY.STALLS_LDM_PENDING' is provided to estimate the exposure of memory accesses..." However I could not find such an event in Ivy Bridge performance events list (Table 19-2) in "Intel 64 and IA-32 Architectures Software Developer's Manual Volumes 3". In fact none of the CYCLE_ACTIVITY.* events mentioned in Optimization Reference Manual exist in the Ivy Bridge events list. Why are these events not documented?

Thanks!

Jim

[Hussam_Mousa__Intel_ · Accepted solution]

Hi Jim,

The events will be appearing in the upcoming revision of the SDM. In the meantime you can use this list for counting these events:

0xA3 0x01 CYCLE_ACTIVITY.CYCLES_L2_PENDING

0xA3 0x08 CYCLE_ACTIVITY.CYCLES_L1D_PENDING

0xA3 0x02 CYCLE_ACTIVITY.CYCLES_LDM_PENDING

0xA3 0x04 CYCLE_ACTIVITY.CYCLES_NO_EXECUTE

0xA3 0x05 CYCLE_ACTIVITY.STALLS_L2_PENDING

0xA3 0x06 CYCLE_ACTIVITY.STALLS_LDM_PENDING

0xA3 0x0C CYCLE_ACTIVITY.STALLS_L1D_PENDING

Regards,
Hussam

[JimH]

Hi Hussam,

Thanks a lot! This is very helpful.

Do these events also work for Sandy Bridge?

Jim

[Hussam_Mousa__Intel_]

Yes, the events apply to Sandy Bridge as well. Future SDM should also reflect this.

[JimH]

Great! Thanks!

[Divino_C_]

Until today the Ivy Bridge PMU Events table (19-5) in SDM 3B is missing the events for CYCLE_ACTIVITY.STALLS_ . These events, however, appear in Intel VTune event list for 3rd generation machines.