Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

Sandy Bridge L2 Writeback to L3, PMC 0xF2

perfwise
Beginner
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Hello,
I am measuring the PMC 0xF2 to get the evictions from the L2 to the L3 due to DEMAND REQUEST and from the L2 HW PREF. In each source, the evictions are reported for CLEAN and DIRTY lines.
What I don't understand is the L3 is inclusive of the data in the L1 or L2, so why are we evicting CLEAN lines to the L3.
If you look and measure the PMC data on PMC 0xF0 you can monitor all L2 -> L3 writebacks, that number does not include the evictions of CLEAN lines but rather the DIRTY component.
On SandyBridge, do you evict clean L2 lines to the L3, I don't believe so, right?
If you don't, then why in Table A2 of the System Prog Guide, do you state PMC 0xF2 umask=0x01,0x04 are measures of this activity?
Thanks for any clarification..
perfwise
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Patrick_F_Intel1
Employee
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Wow... what are you doing... writing a thesis on Sandy Bridge counters?

I'm guessing that the L2 clean line is not copied to L3 (since it is already in theL3)and the line in the L2cache is simply replaced with the data that caused the eviction.
I'll ask someone who knows.
Yes, I would not expect the 0xF0 WB event (L2_TRANS.L2_WB) to count L2 clean evictions.
I'm not sure what the techinal definition of 'eviction' is. I can see that it says "you're outa here" but not that it says what happens to the line next.
Pat
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perfwise
Beginner
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Pat,
Yeah, not a thesis but figuring out how to use my hardware well :o). Yeah, I don't expect these evictions are really happening, because data in the L2 must reside in the L3.
I'll have more questions btw.. so be prepared, and as always thanks again for the help.
perfwise
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