performance counters based on memory objects(data strcutures)

[kai_w_]

Hi,

We notice that VTune Amplifier's Memory Access analysis can attribute performance events to memory objects (data structures) based on performance counters (https://software.intel.com/en-us/memory-access-analysis-lin).

We are wondering if there are any APIs that allow programmers to do the similar thing in a program.

Thank you.

[Dmitry_P_Intel1]

Hello,

VTune uses binary instrumentation of memory allocations/deallocations (based on PIN) to get memory object mapping to data addresses over time. Extracting data linear address from PEBS buffers of precise events allows to correlate them with the memory objects.

May I ask what kind of a use case do you have to get an API on this? Writing your own tool to generate performance reports or get data inside the application to make it more dynamic?

Thanks & Regards, Dmitry

[kai_w_]

Thank you, Dmitry!

You are right. We are developing a runtime to get data inside the application. We use our own implementation of the heap library to keep track of all dynamic memory allocations/deallocations. So mapping memory objects to addresses is not a problem. But, how to associate performance events with data linear address? For example, if we have cache misses, is there any counter that can inform us which accesses to specific addresses cause those cache misses?

Thank you.

dmitry-prohorov (Intel) wrote:

Hello,

VTune uses binary instrumentation of memory allocations/deallocations (based on PIN) to get memory object mapping to data addresses over time. Extracting data linear address from PEBS buffers of precise events allows to correlate them with the memory objects.

May I ask what kind of a use case do you have to get an API on this? Writing your own tool to generate performance reports or get data inside the application to make it more dynamic?

Thanks & Regards, Dmitry

[Dmitry_R_Intel1]

The data linear address comes together with the event. It is a field in the PEBS (Precise Event Based Sampling) record available for some events. So whenever cache miss counter overflowed and you got PMI you can read data address from PEBS which caused that last cache miss which resulted in the overflow. 

Detailed information can be found in the Software Developer's Manual, volume 3, chapter 18.

[kai_w_]

Dmitry Ryabtsev (Intel) wrote:

The data linear address comes together with the event. It is a field in the PEBS (Precise Event Based Sampling) record available for some events. So whenever cache miss counter overflowed and you got PMI you can read data address from PEBS which caused that last cache miss which resulted in the overflow. 

Detailed information can be found in the Software Developer's Manual, volume 3, chapter 18.

Thanks Dmitry, it's really helpful.