Application Acceleration With FPGAs
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Alt_sld_fab_0.alt_sld_fab_0: add_instance: Can't create component type altera_sld_agent_endpoint_tie

khyam
Novice
3,121 Views

Arria 10 GX FPGA


Error (11176): Alt_sld_fab_0.alt_sld_fab_0: add_instance: Can't create component type altera_sld_agent_endpoint_tieoff
Info (11172): invoked from within
Info (11172): "add_instance sldfabric_t0 altera_sld_agent_endpoint_tieoff"
Info (11172): ("eval" body line 32)
Info (11172): invoked from within
Info (11172): "eval $tcl"
Info (11172): (procedure "compose" line 36)
Info (11172): invoked from within
Info (11172): "compose"
Info (11172): invoked from within
Info (11172): "interp eval $slave {
Info (11172): Compose
Info (11172): }"
Error (11176): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.auto_signaltap_add_afu.clock: auto_signaltap_add_afu.clock must be connected to a clock output
Info (11172): ***************************************************************

Info (11172): ***************************************************************
Error (11176): Error opening ../../../build/qdb/_compiler/afu_default/_flat/19.2.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0.ip.

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1 Solution
khyam
Novice
3,068 Views

I have resolved the issue. Please close the request service. Thank you!!!!

View solution in original post

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8 Replies
RichardTanSY_Intel
3,098 Views

Hi @khyam 

 

I found a case with similar error although the user seems to resolve the issue on their own.

https://community.intel.com/t5/Application-Acceleration-With/How-to-correct-the-signal-tap-relative-to-below-error-error-auto/td-p/694631?profile.language=en

May I know what kind of design that are you using to run the compilation? Have you try to run an example design that is available in our Intel website? 

 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

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khyam
Novice
3,095 Views

I used sample example nlb_mode_0_stp, its has signal tap file(.stp). I used mmlink utility of OPAE2.0 for debugging the Arria 10 GX and D5005 PAC card with system console and quartus signal tap tool. The AFU with .stp file compiled successfully and I can see the signal tap instance but receive the following error when trying to acquire data.

"Error (261005): can't find the instance. Download a design with SRAM Object File Containing this instance."

 

When I used my own design, that is integrated with Xeon host processor in OPAE Platform. without Signal tap (.stp) file, it compiled successfully, but when i try to add .stp file instance in my design, I am getting below error.

Error (11176): Alt_sld_fab_0.alt_sld_fab_0: add_instance: Can't create component type altera_sld_agent_endpoint_tieoff

 

Yup looked the post you provide, but he didn't explained, how he resolve the issue.

 

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RichardTanSY_Intel
3,086 Views

Hi @khyam 

 

Could you try to cross check with the user guide flow in step 1 & step 2 and compile the design again?  

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-debug.pdf#page=24

Let me know how it goes. 

 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

 

 

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khyam
Novice
3,069 Views

I have resolved the issue. Please close the request service. Thank you!!!!

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RichardTanSY_Intel
3,054 Views

Hi @khyam 

 

I am glad that you are able to solve the issue. Would you mind to share with us the root cause and the solution to solve this issue? 

This may helps those who come across this issue. 

 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

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RichardTanSY_Intel
3,030 Views

Since the question has been addressed, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

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khyam
Novice
2,995 Views

Solution:

 

Add below command to the afu.qsf file to set stp file

set_global_assignment -name  VERILOG_MACRO "INCLUDE_REMOTE_STP"

then run the design using $run.sh command

or

Add this line to filelist.txt file.

+define+INCLUDE_REMOTE_STP

Then build the design using following command

afu_synth_setup --source filelist.txt build/stp

So, It will add signal tap host instance in the design.

 

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jimlinmake
Beginner
2,986 Views

good sharing

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