Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
504 Discussions

Role of the DIFFIO_RX in FPGA MAX10 10M50DA

MHASI2
Novice
1,598 Views

​What is the main role of the DIFFIO_RX pin in the MAX10 IC itself?

May I know the condition of the IC when the DIFFIO_RX becomes "High" state and vice versa.

Looking forward for the answer.

Thank you.

 

 

 

 

 

 

 

0 Kudos
1 Reply
YuanLi_S_Intel
Employee
1,452 Views

Hi Muhammad,

 

I/O with this DIFFIO_RX means that the I/O can be used for transceiver RX channel. The condition of the FPGA is depending on the design itself since FPGA is configurable.

 

Thank You.

0 Kudos
Reply