Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs
494 Discussions

Total register & logic consumed from Arria 10 PAC

E-Hong
New Contributor I
1,271 Views

Hi,

 

Is there any ways to obtain the amount of register and logic consumed from running inference on the Arria 10 PAC? I am trying to get the sof/pof report like those generated on Quartus when running synthesis.

 

Does programming a bitstream on the Arria 10 PAC generate a report?

 

Thank you.

0 Kudos
2 Replies
EricMunYew_C_Intel
Moderator
1,222 Views

You can find the details from the following:

/build_synth/build/output_files/afu_default.fit.rpt


0 Kudos
E-Hong
New Contributor I
1,189 Views

Hi,

Can I perform this on DevCloud Edge as well? If so, what is the path to the rpt file?

 

Thank you.

0 Kudos
Reply